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* arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker2013-07-151-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the ARM uses of the __cpuinit macros from C code, and all __CPUINIT from assembly code. It also had two ".previous" section statements that were paired off against __CPUINIT (aka .section ".cpuinit.text") that also get removed here. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Russell King <linux@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properlyRussell King2013-04-081-1/+1
| | | | | | | | Let's do the changes properly and fix the same problem everywhere, not just for one case. Cc: <stable@vger.kernel.org> # kernels containing 15e0d9e37c or equivalent Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7542/1: mm: fix cache LoUIS API for xscale and feroceonLorenzo Pieralisi2012-09-281-0/+1
| | | | | | | | | | Some architectures like xscale and feroceon have cache API variants that map cache flushing functions as aliases to the base architecture. This patch adds the required aliases to complete the implementation of cache flushing LoUIS API. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: mm: implement LoUIS API for cache maintenance opsLorenzo Pieralisi2012-09-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM v7 architecture introduced the concept of cache levels and related control registers. New processors like A7 and A15 embed an L2 unified cache controller that becomes part of the cache level hierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable do not require a flush of the entire cache hierarchy to DRAM but just the cache levels belonging to the Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems correspond to L1. The current cache flushing API used in cpu_suspend and __cpu_disable, flush_cache_all(), ends up flushing the whole cache hierarchy since for v7 it cleans and invalidates all cache levels up to Level of Coherency (LoC) which cripples system performance when used in hot paths like hotplug and cpuidle. Therefore a new kernel cache maintenance API must be added to cope with latest ARM system requirements. This patch adds flush_cache_louis() to the ARM kernel cache maintenance API. This function cleans and invalidates all data cache levels up to the Level of Unification Inner Shareable (LoUIS) and invalidates the instruction cache for processors that support it (> v7). This patch also creates an alias of the cache LoUIS function to flush_kern_all for all processor versions prior to v7, so that the current cache flushing behaviour is unchanged for those processors. v7 cache maintenance code implements a cache LoUIS function that cleans and invalidates the D-cache up to LoUIS and invalidates the I-cache, according to the new API. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: proc-*.S: place cpu_reset functions into .idmap.text sectionWill Deacon2011-12-061-0/+3
| | | | | | | | | | | The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: pm: only use preallocated page table during resumeRussell King2011-09-211-11/+10
| | | | | | | | | | | Only use the preallocated page table during the resume, not while suspending. This avoids the overhead of having to switch unnecessarily to the resume page table in the suspend path. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: pm: preallocate a page table for suspend/resumeRussell King2011-09-211-4/+0
| | | | | | | | | | | Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Fix build errors caused by adding generic macrosRussell King2011-07-211-3/+0
| | | | | | | | | | | | | Commit 66a625a (ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macros) introduced build errors when PM_SLEEP is not enabled. The per-CPU do_suspend/do_resume functions are defined via the preprocessor to constant 0. However, the macros which use these were converted to assembly, resulting in undefined references to these functions. Fix that by moving the ! ifdef section into proc-macros.S and deleting it from all effected proc-*.S files. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: mm: proc-xscale: Use new generic struct definition macrosDave Martin2011-07-071-431/+76
| | | | | | | | | | | Without this patch, xscale_80200_A0_A1 is missing the icache_flush_all entry, which would result in the wrong functions being called at run-time. This patch re-uses xscale_icache_flush_all for xscale_80200_A0_A1_cache_fns. Signed-off-by: Dave Martin <dave.martin@linaro.org>
* ARM: Fix .size directive for xscale_dma_a0_map_areaBen Hutchings2011-04-281-1/+1
| | | | | | | | | gas used to accept (and ignore?) .size directives which referred to undefined symbols, as this does. In binutils 2.21 these are treated as fatal errors. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* ARM: Make consolidated PM sleep code depend on PM_SLEEPRussell King2011-04-021-1/+1
| | | | | | | | | | | | CONFIG_PM is now set whenever we support either runtime PM in addition to suspend and hibernate. This causes build errors when runtime PM is enabled on a platform, but the CPU does not have the appropriate support for suspend. So, switch this code to use CONFIG_PM_SLEEP rather than CONFIG_PM to allow runtime PM to be enabled without causing build errors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: pm: add generic CPU suspend/resume supportRussell King2011-02-221-2/+43
| | | | | | | | | | | This adds core support for saving and restoring CPU coprocessor registers for suspend/resume support. This contains support for suspend with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Tested-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: pgtable: provide RDONLY page table bit rather than WRITE bitRussell King2010-12-221-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6466/1: implement flush_icache_all for the rest of the CPUsMika Westerberg2010-10-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 81d11955bf0 ("ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns: flush_icache_all(). It also implemented this for v6 and v7 but not for v5 and backwards. Without the function pointer in place, we will be calling wrong cache functions. For example with ep93xx we get following: Unable to handle kernel paging request at virtual address ee070f38 pgd = c0004000 [ee070f38] *pgd=00000000 Internal error: Oops: 80000005 [#1] PREEMPT last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36+ #1) PC is at 0xee070f38 LR is at __dma_alloc+0x11c/0x2d0 pc : [<ee070f38>] lr : [<c0032c8c>] psr: 60000013 sp : c581bde0 ip : 00000000 fp : c0472000 r10: c0472000 r9 : 000000d0 r8 : 00020000 r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000 r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: c000717f Table: c0004000 DAC: 00000017 Process swapper (pid: 1, stack limit = 0xc581a270) [<c0032c8c>] (__dma_alloc+0x11c/0x2d0) [<c0032e5c>] (dma_alloc_writecombine+0x1c/0x24) [<c0204148>] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60) [<c02041c0>] (ep93xx_pcm_new+0x5c/0x88) [<c01ff188>] (snd_soc_instantiate_cards+0x8a8/0xbc0) [<c01ff59c>] (soc_probe+0xfc/0x134) [<c01adafc>] (platform_drv_probe+0x18/0x1c) [<c01acca4>] (driver_probe_device+0xb0/0x16c) [<c01ac284>] (bus_for_each_drv+0x48/0x84) [<c01ace90>] (device_attach+0x50/0x68) [<c01ac0f8>] (bus_probe_device+0x24/0x44) [<c01aad7c>] (device_add+0x2fc/0x44c) [<c01adfa8>] (platform_device_add+0x104/0x15c) [<c0015eb8>] (simone_init+0x60/0x94) [<c0021410>] (do_one_initcall+0xd0/0x1a4) __dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up calling dmac_flush_range(). Now since the entries in the arm920_cache_fns are shifted by one, we jump into address 0xee070f38 which is actually next instruction after the arm920_cache_fns structure. So implement flush_icache_all() for the rest of the supported CPUs using a generic 'invalidate I cache' instruction. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: hotplug cpu: Keep processor information, startup code & ↵Russell King2010-10-081-1/+1
| | | | | | | | | | | __lookup_processor_type When hotplug CPU is enabled, we need to keep the list of supported CPUs, their setup functions, and __lookup_processor_type in place so that we can find and initialize secondary CPUs. Move these into the __CPUINIT section. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Factor out common code from cpu_proc_fin()Russell King2010-07-271-5/+1
| | | | | | | | | | | | | | All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: dma-mapping: remove dmac_clean_range and dmac_inv_rangeRussell King2010-02-151-6/+2
| | | | | | | These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: dma-mapping: provide per-cpu type map/unmap functionsRussell King2010-02-151-0/+41
| | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
* ARM: add size argument to __cpuc_flush_dcache_pageRussell King2009-12-141-6/+7
| | | | | | | ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()Kirill A. Shutemov2009-10-021-1/+1
| | | | | | | | | | | | | | | | | Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Nicolas Pitre has a new email addressNicolas Pitre2009-09-151-1/+1
| | | | | | | | Due to problems at cam.org, my nico@cam.org email address is no longer valid. FRom now on, nico@fluxnic.net should be used instead. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-011-1/+1
| | | | | | asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-011-1/+1
| | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Update Xscale and Xscale3 PTE mappingsRussell King2008-10-011-1/+1
| | | | | | | Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-011-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert Xscale and Xscale3 to use new memory typesRussell King2008-10-011-24/+28
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-011-25/+5
| | | | | | | There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-241-1/+1
| | | | | | | | | | The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Add a prefetch abort handlerPaul Brook2008-04-181-0/+1
| | | | | | | | | This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] 4864/1: Enable write buffer coalescing on IOPArnaud Patard2008-03-201-0/+4
| | | | | | | | Some bootloaders are disabling write buffer coalescing. Enable it back under linux. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4311/1: ixp4xx: add KIXRP435 platformRuslan V. Sushko2007-04-211-0/+28
| | | | | | | | | | Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4100/1: iop3xx: fix cpu mask for iop333Dan Williams2007-01-241-1/+1
| | | | | | | | cosmetic fix so iop333 is not reported as ixp46x iop333 cpuid = 0x69054210 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Unuse another Linux PTE bitRussell King2006-12-131-3/+3
| | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3881/4: xscale: clean up cp0/cp1 handlingLennert Buytenhek2006-12-031-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Include asm/elf.h instead of asm/procinfo.hRussell King2006-11-301-1/+1
| | | | | | | These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3912/1: Make PXA270 advertise HWCAP_IWMMXT capabilityPaul Gortmaker2006-11-021-1/+1
| | | | | | | | | | | | | ARM patch 3756/1 added HWCAP_IWMMXT. This patch adds support for broadcasting that info via /proc/cpuinfo and sets it for the CPU features of the PXA270. I've booted 19rc3 on a pxa270 and confirmed that the /proc/cpuinfo shows "iwmmxt" in the Features. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3814/1: move 80200 dma_inv_range() erratum check out of lineLennert Buytenhek2006-09-251-6/+52
| | | | | | | | | | | | | | | On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't clear the dirty bits, which means that if we invalidate a dirty line, the dirty data can still be written back to memory later on. To work around this, dma_inv_range() on these two processors is implemented as dma_flush_range() (i.e. do a clean D-cache line before doing the invalidate D-cache line.) For this, we currently have a processor ID check in xscale_dma_inv_range(), but a better solution is to add a separate cache_fns and proc_info for A0/A1 80200. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3780/1: Fix iop321 cpuidDan Williams2006-09-141-1/+1
| | | | | | | | | Patch from Dan Williams commit a6a38a66224c7c578cfed2f584b440c81af0c3ae changed the iop321 id to a value that does not work with all platforms. Change the mask to permit bit 11. Tested on an iq80321 600Mhz CRB. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32xLennert Buytenhek2006-07-291-1/+29
| | | | | | | | | | | | | | | Patch from Lennert Buytenhek The IOP 80219 xscale CPU is a stripped down version of the IOP32x. But the fact that the 80219 and IOP32x are very similar doesn't mean that they need to share a cpu table entry. It's also somewhat confusing for the end user to see the 80219 reported as an IOP32x, so this patch splits the IOP32x cpu table entry to make a separate entry for the 80219. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3541/2: workaround for PXA27x erratum E7Nicolas Pitre2006-07-011-1/+7
| | | | | | | | | | | | | | | Patch from Nicolas Pitre According to the Intel PXA27x Processor Family Specification Update document (doc.nr. 280071-009) erratum E7, some care must be taken to locate the disabling and re-enabling of the MMU to the beginning of a cache line to avoid problems in some circumstances. Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this up. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu branchRussell King2006-07-011-9/+7
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| * [ARM] nommu: provide a way for correct control register value selectionRussell King2006-06-291-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Set bit 4 on section mappings correctly depending on CPURussell King2006-06-291-1/+38
|/ | | | | | | | | | | | | | On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu treeRussell King2006-03-251-0/+1
|\ | | | | | | | | | | Fix merge conflict in arch/arm/mm/proc-xscale.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.hRussell King2006-03-211-0/+1
| | | | | | | | | | | | | | Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Remove unnecessary asm/hardware.h includesRussell King2006-03-211-1/+0
|/ | | | | | | | | asm/hardware.h is not required for the majority of processor support files, ioremap support, mm initialisation, acorn IO support, nor the debug code (which picks up its machine specific includes via debug-macros.S) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_rangeNicolas Pitre2006-02-011-5/+11
| | | | | | | | | | Patch from Nicolas Pitre The mini I-cache issue is valid only for kernel space since debuggers would not fly if they used user space addresses for their stubs. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck`Ben Dooks2005-09-201-1/+1
| | | | | | | | | | | Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2839/1: Remove XScale cache and TLB locking codeDeepak Saxena2005-08-031-136/+0
| | | | | | | | | | | Patch from Deepak Saxena The XScale locking code is not something that has been validated on 2.6 and needs to be replaced with a more generic API to use with other ARMs that support locking features. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-171-0/+934
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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