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* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-076-6/+6
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixesRussell King2008-08-071-0/+8
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| * Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-08-036-37/+213
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 5182/1: pxa: Fix pcm990 compilation [ARM] Fix explicit asm(-arm)?/arch-foo references [ARM] move include/asm-arm to arch/arm/include/asm [ARM] Remove explicit dependency for misc.o from compressed/Makefile [ARM] initrd: claim initrd memory exclusively [ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2) [ARM] 5180/1: at91: Fix at91_nand -> atmel_nand rename fallout [ARM] add Sascha Hauer as Freescale i.MX Maintainer [ARM] i.MX: add missing clock functions exports [ARM] i.MX: remove set_imx_fb_info() export [ARM] mx1ads: make mmc platform data available for modules [ARM] mx2: add missing Kconfig dependency
| * \ Merge branch 'linus' into core/generic-dma-coherentIngo Molnar2008-07-294-22/+26
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/Kconfig Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | ARM: support generic per-device coherent dma memDmitry Baryshkov2008-07-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | | [ARM] Remove asm/hardware.h, use asm/arch/hardware.h insteadRussell King2008-08-076-6/+6
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | Remove includes of asm/hardware.h in addition to asm/arch/hardware.h. Then, since asm/hardware.h only exists to include asm/arch/hardware.h, update everything to directly include asm/arch/hardware.h and remove asm/hardware.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-022-2/+2
| | | | | | | | | | | | | | | | | | | | | Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] initrd: claim initrd memory exclusivelyRussell King2008-07-301-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Claim the initrd memory exclusively, and order other memory reservations beforehand. This allows us to determine whether the initrd memory was overwritten, and disable the initrd in that case. This avoids a 'bad page state' bug. Tested-by: Ralph Siemsen <ralphs@netwinder.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2)Eric Miao2008-07-293-22/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (20072fd0c93349e19527dd2fa9588b4335960e62 lost most of its changes somehow, came from a mbox archive applied with git-am. No idea what happened. This puts back the missing bits. --rmk) The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] mx2: add missing Kconfig dependencySascha Hauer2008-07-281-1/+1
| |/ |/| | | | | | | | | | | | | | | It seems this small label was lost in the last merge. Without it no CPU type is selected for the MX2 family of processors. And a build will fail badly... Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | [ARM] Fix shared mmap when more than two maps of the same file existRussell King2008-07-271-3/+7
| | | | | | | | | | | | | | | | | | The shared mmap code works fine for the test case, which only checked for two shared maps of the same file. However, three shared maps result in one mapping remaining cached, resulting in stale data being visible via that mapping. Fix this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | mm: drop unneeded pgdat argument from free_area_init_node()Johannes Weiner2008-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | free_area_init_node() gets passed in the node id as well as the node descriptor. This is redundant as the function can trivially get the node descriptor itself by means of NODE_DATA() and the node's id. I checked all the users and NODE_DATA() seems to be usable everywhere from where this function is called. Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | mm: move bootmem descriptors definition to a single placeJohannes Weiner2008-07-241-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a lot of places that define either a single bootmem descriptor or an array of them. Use only one central array with MAX_NUMNODES items instead. Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Richard Henderson <rth@twiddle.net> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Kyle McMartin <kyle@parisc-linux.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Christoph Lameter <cl@linux-foundation.org> Cc: Mel Gorman <mel@csn.ul.ie> Cc: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'pxa' into develRussell King2008-07-131-0/+2
|\ \ | |/ |/| | | | | | | | | Conflicts: arch/arm/configs/em_x270_defconfig arch/arm/configs/xm_x270_defconfig
| * [ARM] pxa: add support for L2 outer cache on XScale3Eric Miao2008-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'imx' into develRussell King2008-07-101-2/+15
|\ \ | | | | | | | | | | | | | | | Conflicts: arch/arm/mm/Kconfig
| * | i.MX2 family: Add basic mach supportJuergen Beisert2008-07-051-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | This patch adds basic mach support for the mx2 processor family, based on the original freescale code and adapted to mainline kernel coding style. This part adds the global build only. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
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*-------. \ Merge branches 'at91', 'dyntick', 'ep93xx', 'iop', 'ixp', 'misc', 'orion', ↵Russell King2008-07-106-30/+559
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | | | | | | | 'omap-reviewed', 'rpc', 'rtc' and 's3c' into devel
| | | | | * [ARM] Feroceon: don't disable BPU on bootSaeed Bishara2008-07-081-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Feroceon platforms that have a branch prediction unit, bit 11 of the cp15 control register controls the BPU. This patch keeps the old value of this bit instead of always clearing it. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | | | | * [ARM] add Marvell 78xx0 ARM SoC supportStanislav Samsonov2008-06-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: 88fr571-vd supportLennert Buytenhek2008-06-221-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Feroceon 88fr571-vd CPU core as found in e.g. the Marvell Discovery Duo family of ARM SoCs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] add Marvell Kirkwood (88F6000) SoC supportSaeed Bishara2008-06-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: 88fr131 supportLennert Buytenhek2008-06-221-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Shiva 88fr131 CPU core as found in e.g. the Marvell Kirkwood family of ARM SoCs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: L2 cache supportLennert Buytenhek2008-06-224-1/+354
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: L1 cache range operation supportStanislav Samsonov2008-06-221-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] add Marvell Loki (88RC8480) SoC supportLennert Buytenhek2008-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: allow more old Feroceon IDsKe Wei2008-06-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple more Feroceon-based SoCs out in the field that use different Variant and Architecture fields in their Main ID registers -- this patch tweaks the processor match/mask in proc-feroceon.S to catch those SoCs as well. Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: speed up flushing of the entire cacheNicolas Pitre2008-06-221-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing the L1 D cache with a test/clean/invalidate loop is very easy in software, but it is not the quickest way of doing it, as there is a lot of overhead involved in re-scanning the cache from the beginning every time we hit a dirty line. This patch makes proc-feroceon.S use "clean+invalidate by set/way" loops according to possible cache configuration of Feroceon CPUs (either direct-mapped or 4-way set associative). Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
| | | | | * [ARM] Feroceon: annotate 88fr531-vd CPU entriesLennert Buytenhek2008-06-221-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Annotate the entries for the 88fr531-vd CPU core in arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S with the full name of the core. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
| | | | | * [ARM] Orion: fix various whitespace and coding style issuesLennert Buytenhek2008-06-221-4/+4
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More cosmetic cleanup: - Replace 8-space indents by proper tab indents. - In structure initialisers, use a trailing comma for every member. - Collapse "},\n{" in structure initialiers to "}, {". Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <linux@arm.linux.org.uk>
| | | | * [ARM] 5092/1: Fix the I-cache invalidation on ARMv6 and later CPUsCatalin Marinas2008-07-032-0/+6
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the I-cache invalidation in update_mmu_cache if the corresponding vma is marked as executable. It also invalidates the I-cache if a thread migrates to a CPU it never ran on. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 5130/4: Support for the at91sam9g20sedji gaouaou2008-07-101-2/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337 Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com> Signed-off-by: Justin Waters <justin.waters@timesys.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / / [ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT modeLennert Buytenhek2008-05-174-4/+4
|/ / | | | | | | | | | | | | | | | | | | | | The CPU's dma_flush_range() operation needs to clean+invalidate the given memory area if the cache is in writeback mode, or do just the invalidate part if the cache is in writethrough mode, but the current proc-arm{925,926,940,946} (incorrectly) do a cache clean in the latter case. This patch fixes that. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | arm: Export empty_zero_page for ZERO_PAGE usage in modules.Aneesh Kumar K.V2008-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | ext4 uses ZERO_PAGE(0) to zero out blocks. We need to export different symbols in different arches for the usage of ZERO_PAGE in modules. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: "Theodore Ts'o" <tytso@mit.edu>
* | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2008-04-304-50/+113
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (26 commits) [ARM] pxa: fix 1c104e0e4f6ab396960c058e95e18bdedcac945b [ARM] serial: s3c2410: platform_get_irq() may return signed unnoticed [ARM] am79c961a: platform_get_irq() may return signed unnoticed [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page() [ARM] Feroceon: fix function alignment in proc-feroceon.S [ARM] Orion: catch a couple more alternative spellings of PCIe [ARM] Orion: fix orion-ehci platform resource end addresses [ARM] Orion: fix ->map_irq() PCIe bus number check [ARM] Orion: fix ioremap() optimization [ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check kprobes/arm: fix decoding of arithmetic immediate instructions kprobes/arm: fix cache flush address for instruction stub [ARM] 5022/1: Race in ARM MMCI PL18x driver, V2 [ARM] 5021/1: at91: buildfix for sam9263 + PM [ARM] 5018/1: RealView: Fix the ARM11MPCore Oprofile compilation [ARM] 5016/1: AT91: typo in mci configuration for at91cap at91sam9263 [ARM] 5017/1: pxa3xx: Report unsupported wakeup sources in pxa3xx_set_wake() [ARM] 5020/1: magician: remove __devinit marker from pasic3_leds_info [ARM] 5014/1: Cleanup reset state before entering suspend or resetting. ...
| * | [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()Lennert Buytenhek2008-04-284-3/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a set of Feroceon-specific {copy,clear}_user_page() routines that perform more optimally than the generic implementations. This also deals with write-allocate caches (Feroceon can run L1 D in WA mode) which otherwise prevents Linux from booting. [nico: optimized the code even further] Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Tested-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] Feroceon: fix function alignment in proc-feroceon.SNicolas Pitre2008-04-281-3/+10
| | | | | | | | | | | | | | | | | | One overzealous .align 10 fixed, and a few .align5 added. Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN checkLennert Buytenhek2008-04-281-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Feroceon cache replacement policy is always pseudorandom (and the relevant control register bit is ignored), remove the CONFIG_CPU_CACHE_ROUND_ROBIN check from proc-feroceon.S. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH checkLennert Buytenhek2008-04-282-41/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the Feroceon doesn't have a global WT override bit like ARM926 does, remove all code relating to this mode of operation from proc-feroceon.S. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | | iomap: fix 64 bits resources on 32 bitsBenjamin Herrenschmidt2008-04-291-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all implementations of pci_iomap() in the kernel, including the generic lib/iomap.c one, copies the content of a struct resource into unsigned long's which will break on 32 bits platforms with 64 bits resources. This fixes all definitions of pci_iomap() to use resource_size_t. I also "fixed" the 64bits arch for consistency. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-2423-17/+29
| | | | | | | | | | | | | | | | | | | | The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*---. \ Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', ↵Russell King2008-04-192-3/+1
|\ \ \ \ | | |_|/ | |/| | | | | | 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel
| | | * Orion: orion -> orion5x renameLennert Buytenhek2008-03-271-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e. not the plat-orion bits.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * [ARM] remove redundant display of free swap space in show_mem()Johannes Weiner2008-04-191-2/+0
| |/ | | | | | | | | | | Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Allow the L2X0 outer cache support to be configurableCatalin Marinas2008-04-181-1/+5
| | | | | | | | | | | | | | | | | | | | By default, this option was selected by the platform Kconfig. This patch adds "depends on" to L2X0 so that it can be enabled/disabled manually. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | RealView: Add the configuration and build changes for PB1176Bahadir Balban2008-04-181-1/+1
| | | | | | | | | | | | | | | | | | This patch enables the building of Linux for the PB1176 platform. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | RealView: Enable the configuration options for PB11MPCoreBahadir Balban2008-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the PB11MPCore support to the corresponding Kconfig and Makefile to enable building. Signed-off-by: Bahadir Balban <bahadir.balban@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | RealView: Allow ARMv7 support for RealView/EBCatalin Marinas2008-04-181-1/+1
| | | | | | | | | | | | | | | | This patch changes the CPU_V7 configuration dependency to allow MACH_REALVIEW_EB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | RealView: Move the SCU initialisation out of __v6_setupCatalin Marinas2008-04-181-14/+0
| | | | | | | | | | | | | | | | | | This patch moves the SCU initialisation from __v6_setup to the smp_prepare_cpus() function as it relies on platform-specific settings. Changes to get_core_count() are mainly for allowing cleaner code with the upcoming PB11MPCore patches. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | Add a prefetch abort handlerPaul Brook2008-04-1817-0/+40
| | | | | | | | | | | | | | | | | | This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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