summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/amlogic/meson-a1.dtsi (follow)
Commit message (Collapse)AuthorAgeFilesLines
* arch: arm64: dts: meson: a1: add assigned-clocks for usb nodeAlexey Romanov2024-02-131-0/+2
| | | | | | | | | | | | | To ensure proper functionality of USB, it is necessary to use the rate of 64000000 for CLKID_USB_BUS. For instance, adb may not function correctly without this setting. This information has been derived from the vendor SDK. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240124130623.3471236-1-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: a1: support all i2c masters and their muxesDmitry Rokosov2023-10-091-0/+144
| | | | | | | | | | | A1 SoC family has four i2c masters: i2c0 (I2CM_A), i2c1 (I2CM_B), i2c2 (I2CM_C) and i2c3 (I2CM_D). Signed-off-by: George Stark <gnstark@salutedevices.com> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231006114145.18718-1-ddrokosov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: Add SPIFC mux pinsIgor Prusov2023-10-061-0/+12
| | | | | | | | | | SPI Flash Controller uses multi-function pins, so add missing mux definition. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231005195543.380273-2-ivprusov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: add ao secure nodeAlexey Romanov2023-09-111-0/+6
| | | | | | | | | | | | | | | Add node for board info registers, which allows getting SoC family and board revision. For example, with MESON_GX_SOCINFO config enabled we can get the following information for board with Meson A1 SoC: soc soc0: Amlogic Meson A1 (A113L) Revision 2c:a (1:a) Detected Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-14-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: add hw rng nodeAlexey Romanov2023-09-111-0/+6
| | | | | | | | | | | Add hardware number generator node. HWRNG access requires OTP power domain being enabled. Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-13-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: add saradc definitionGeorge Stark2023-09-111-0/+16
| | | | | | | | | | | Add saradc node to Amlogic Meson A1 SoC main dtsi. Saradc is Successive Approximation Register (SAR) A/D Converter. Signed-off-by: George Stark <GNStark@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-12-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: add eMMC controller and its pinsJan Dakinevich2023-09-111-0/+43
| | | | | | | | | | | | | | | | | | The definition is inspired by a similar one for AXG SoC family. 'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as "default" and "clk-gate" in board-specific device trees. During initialization 'meson-gx' driver sets clock to safe low-frequency value (400kHz). However, both source clocks ("clkin0" and "clkin1") are high-frequency by default, and using of eMMC's internal divider is not enough to achieve so low values. To provide low-frequency source, reparent "sd_emmc_sel2" clock using 'assigned-clocks' property. Signed-off-by: Jan Dakinevich <yvdakinevich@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-11-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: introduce UART_AO mux definitionsOleg Lyovin2023-09-111-0/+16
| | | | | | | | | | | | | The Amlogic A1 has a UART_AO port, which can be used, for example, for BT HCI H4 connection. This patch adds mux definitions for it. Signed-off-by: Oleg Lyovin <ovlevin@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-10-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: introduce SPI Flash ControllerMartin Kurbanov2023-09-111-0/+10
| | | | | | | | | | This controller can be used for spinand flash connection. Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-9-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: enable efuse controller and setup its clkAlexey Romanov2023-09-111-0/+9
| | | | | | | | | | EFUSE A1 controller uses CLKID_OTP clock and PWRC_OTP_ID power domain. Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-8-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: support USB controller in OTG modeDmitry Rokosov2023-09-111-0/+59
| | | | | | | | | | | | | Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3 heads. It supports otg/host/peripheral modes. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-7-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: introduce PLL and Peripherals clk controllersDmitry Rokosov2023-09-111-0/+26
| | | | | | | | | | | | This patch adds clkc and clkc_pll dts nodes to A1 SoC main dtsi. The first one is responsible for all SoC peripherals clocks excluding audio clocks. The second one is used by A1 SoC PLLs. Actually, there are two different APB heads, so we have two different drivers. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-6-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: reorder gpio_intc node definitionDmitry Rokosov2023-09-111-10/+10
| | | | | | | | | | | It is recommended to maintain a sorted order of device tree entries, so move the gpio_intc node ahead of the uart_AO node. Fixes: ea254644a228 ("arm64: dts: meson-a1: add gpio_intc node") Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-5-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: remove the unnecessary 'okay' status pwrc valueDmitry Rokosov2023-09-111-1/+0
| | | | | | | | | | | In the file 'meson-a1.dtsi,' which is a basic device tree include, it is not necessary to mark the node with 'status = "okay"' because it is enabled by default. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-4-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: remove extra empty line before reset nodeDmitry Rokosov2023-09-111-1/+0
| | | | | | | | | | There should be only one empty line between device tree node definitions. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-3-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: reorder includes to keep them sortedDmitry Rokosov2023-09-111-2/+2
| | | | | | | | | | It is recommended to alphabetically sort all headers included in the dtsi. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230823213630.12936-2-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: a1: change uart compatible stringDmitry Rokosov2023-07-251-2/+2
| | | | | | | | | | | | | | In the current implementation, the meson-a1 configuration incorporates a unique compatibility tag "amlogic,meson-a1-uart' within the meson-uart driver due to its usage of the new console device name "ttyS". Consequently, the previous compatibility tag designated for the 'amlogic,meson-gx-uart' configuration has become obsolete and is no longer relevant to the current setup. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230705181833.16137-8-ddrokosov@sberdevices.ru Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: amlogic: add missing cache propertiesKrzysztof Kozlowski2023-05-091-0/+1
| | | | | | | | | | | | As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson-a1: add gpio_intc nodeAlexey Romanov2023-03-071-0/+10
| | | | | | | | | | Add gpio interrupt controller node. Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230202141520.40003-1-avromanov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: Update cache properties for amlogicPierre Gondois2022-11-071-0/+1
| | | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221107155825.1644604-4-pierre.gondois@arm.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: amlogic: misc DT schema fixupsKevin Hilman2021-04-221-2/+2
| | | | | | | | | | Take a pass at cleaning up a bunch of warnings from 'make dtbs_check' that have crept in. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210421204833.18523-1-khilman@baylibre.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: meson: a1: add secure power domain controllerJianxin Pan2020-02-141-0/+6
| | | | | | | | Enable power domain controller for Meson A1 SoC. Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Link: https://lore.kernel.org/r/1579087831-94965-5-git-send-email-jianxin.pan@amlogic.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: a1: add pinctrl controller supportQianggui Song2019-12-101-0/+19
| | | | | | | | add peripheral pinctrl controller to a1 SoC Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: add reset controller for Meson-A1 SoCXingyu Chen2019-12-101-0/+6
| | | | | | | | Add the reset controller device of Meson-A1 SoC family Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: add support for A1 based Amlogic AD401Jianxin Pan2019-10-071-0/+130
Add basic support for the Amlogic A1 based Amlogic AD401 board: which describe components as follows: Reserve Memory, CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-19 03:53:13 +0100