linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	arm64: xilinx: Put ethernet phys to mdio node	Michal Simek	2023-12-13	1	-11/+15
\| \| \| \| \| \| \| \| \|	All zynqmp boards have been already described via mdio node that's why also convert zc1751. With using mdio node there is an option to add reset property for the whole mdio bus. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
*	arm64: zynqmp: Set qspi tx-buswidth to 4	Amit Kumar Mahapatra	2023-06-05	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \|	All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
*	arm64: zynqmp: Switch to amd.com emails	Michal Simek	2023-06-05	1	-1/+1
\| \| \| \| \| \| \| \| \|	Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
*	arm64: zynqmp: Add mali-400 gpu node for zynqmp	Parth Gajjar	2023-05-12	1	-0/+4
\| \| \| \| \| \| \| \| \| \|	Add mali-400 gpu node for zynqmp. Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar <parth.gajjar@amd.com> Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
*	arm64: zynqmp: Wire qspi on multiple boards	Michal Simek	2021-09-13	1	-0/+14
\| \| \| \| \| \| \| \|	Couple of boards have qspi on the board that's why enable controller and describe them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
*	arm64: zynqmp: Wire DP and DPDMA for dc1/dc4	Michal Simek	2021-09-13	1	-1/+9
\| \| \| \| \| \| \|	Enable Display Port and Display Port DMA for zc1751 dc1 and dc4. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/dbbd212bcc587e835d6df2f91622f5baa124bff5.1623684253.git.michal.simek@xilinx.com
*	arm64: dts: xilinx: Add the clock nodes for zynqmp	Rajan Vaja	2020-01-09	1	-2/+2
\| \| \| \| \| \| \|	Add clock nodes for zynqmp based on CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
*	arm64: zynqmp: Add support for Xilinx zc1751	Michal Simek	2018-03-08	1	-0/+178
	Xilinx zc1751 boards is used for silicon validation. Board can be extended with 5 FMCs/DCs cards to connect various IPs. Describe all these combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org>