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Commit message (
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Author
Age
Files
Lines
*
arm64/sme: Identify supported SME vector lengths at boot
Mark Brown
2022-04-22
1
-0
/
+3
*
arm64/sme: Basic enumeration support
Mark Brown
2022-04-22
1
-0
/
+1
*
arm64: add ID_AA64ISAR2_EL1 sys register
Joey Gouly
2021-12-13
1
-0
/
+1
*
arm64: cpuinfo: Split AArch32 registers out into a separate struct
Will Deacon
2021-06-11
1
-21
/
+25
*
arm64: Check if GMID_EL1.BS is the same on all CPUs
Catalin Marinas
2021-05-26
1
-0
/
+1
*
arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
Catalin Marinas
2021-05-26
1
-5
/
+5
*
arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
Anshuman Khandual
2020-05-21
1
-0
/
+1
*
arm64/cpufeature: Introduce ID_MMFR5 CPU register
Anshuman Khandual
2020-05-21
1
-0
/
+1
*
arm64/cpufeature: Introduce ID_DFR1 CPU register
Anshuman Khandual
2020-05-21
1
-0
/
+1
*
arm64/cpufeature: Introduce ID_PFR2 CPU register
Anshuman Khandual
2020-05-21
1
-0
/
+1
*
arm64: Introduce ID_ISAR6 CPU register
Anshuman Khandual
2020-01-15
1
-0
/
+1
*
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
Thomas Gleixner
2019-06-19
1
-12
/
+1
*
arm64/sve: Probe SVE capabilities and usable vector lengths
Dave Martin
2017-11-03
1
-0
/
+4
*
arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs
Steve Capper
2016-07-12
1
-0
/
+2
*
arm64: add ARMv8.2 id_aa64mmfr2 boiler plate
James Morse
2016-02-18
1
-0
/
+1
*
arm64: Consolidate CPU Sanity check to CPU Feature infrastructure
Suzuki K. Poulose
2015-10-21
1
-1
/
+2
*
arm64: Keep track of CPU feature registers
Suzuki K. Poulose
2015-10-21
1
-0
/
+1
*
arm64: Move mixed endian support detection
Suzuki K. Poulose
2015-10-21
1
-0
/
+2
*
arm64: sanity checks: add missing AArch32 registers
Mark Rutland
2015-01-07
1
-0
/
+5
*
arm64: sanity checks: add ID_AA64DFR{0,1}_EL1
Mark Rutland
2014-11-25
1
-0
/
+2
*
arm64: cpuinfo: record cpu system register values
Mark Rutland
2014-07-18
1
-0
/
+59