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path: root/arch/arm64/include/asm/cpu.h (follow)
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* arm64/sme: Identify supported SME vector lengths at bootMark Brown2022-04-221-0/+3
* arm64/sme: Basic enumeration supportMark Brown2022-04-221-0/+1
* arm64: add ID_AA64ISAR2_EL1 sys registerJoey Gouly2021-12-131-0/+1
* arm64: cpuinfo: Split AArch32 registers out into a separate structWill Deacon2021-06-111-21/+25
* arm64: Check if GMID_EL1.BS is the same on all CPUsCatalin Marinas2021-05-261-0/+1
* arm64: Change the cpuinfo_arm64 member type for some sysregs to u64Catalin Marinas2021-05-261-5/+5
* arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 contextAnshuman Khandual2020-05-211-0/+1
* arm64/cpufeature: Introduce ID_MMFR5 CPU registerAnshuman Khandual2020-05-211-0/+1
* arm64/cpufeature: Introduce ID_DFR1 CPU registerAnshuman Khandual2020-05-211-0/+1
* arm64/cpufeature: Introduce ID_PFR2 CPU registerAnshuman Khandual2020-05-211-0/+1
* arm64: Introduce ID_ISAR6 CPU registerAnshuman Khandual2020-01-151-0/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-12/+1
* arm64/sve: Probe SVE capabilities and usable vector lengthsDave Martin2017-11-031-0/+4
* arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfsSteve Capper2016-07-121-0/+2
* arm64: add ARMv8.2 id_aa64mmfr2 boiler plateJames Morse2016-02-181-0/+1
* arm64: Consolidate CPU Sanity check to CPU Feature infrastructureSuzuki K. Poulose2015-10-211-1/+2
* arm64: Keep track of CPU feature registersSuzuki K. Poulose2015-10-211-0/+1
* arm64: Move mixed endian support detectionSuzuki K. Poulose2015-10-211-0/+2
* arm64: sanity checks: add missing AArch32 registersMark Rutland2015-01-071-0/+5
* arm64: sanity checks: add ID_AA64DFR{0,1}_EL1Mark Rutland2014-11-251-0/+2
* arm64: cpuinfo: record cpu system register valuesMark Rutland2014-07-181-0/+59