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path: root/arch/arm64/include/asm/tlbflush.h (follow)
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* arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGESGavin Shan2024-04-111-2/+2
* arm64: tlb: Improve __TLBI_VADDR_RANGE()Gavin Shan2024-04-111-11/+18
* arm64: tlb: Fix TLBI RANGE operandGavin Shan2024-04-101-9/+11
* arm64/mm: dplit __flush_tlb_range() to elide trailing DSBRyan Roberts2024-02-231-2/+11
* arm64/mm: Update tlb invalidation routines for FEAT_LPA2Ryan Roberts2023-11-271-32/+58
* arm64/mm: Modify range-based tlbi to decrement scaleRyan Roberts2023-11-271-10/+10
* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2023-11-031-4/+4
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| * arm64: tlbflush: Rename MAX_TLBI_OPSOliver Upton2023-09-221-4/+4
* | arm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_REPEAT_TLBIMark Rutland2023-10-161-3/+2
* | arm64: Avoid cpus_have_const_cap() for ARM64_HAS_ARMv8_4_TTLMark Rutland2023-10-161-1/+1
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* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2023-09-071-53/+71
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| * arm64: tlb: Implement __flush_s2_tlb_range_op()Raghavendra Rao Ananta2023-08-171-0/+3
| * arm64: tlb: Refactor the core flush algorithm of __flush_tlb_rangeRaghavendra Rao Ananta2023-08-171-53/+68
* | arm64: tlbflush: add some comments for TLB batched flushingYicong Yang2023-08-211-0/+15
* | mmu_notifiers: rename invalidate_range notifierAlistair Popple2023-08-181-3/+3
* | mmu_notifiers: call invalidate_range() when invalidating TLBsAlistair Popple2023-08-181-0/+5
* | arm64: support batched/deferred tlb shootdown during page reclamation/migrationBarry Song2023-08-181-3/+41
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* arm64: mm: Fix TLBI vs ASID rolloverWill Deacon2021-08-061-5/+6
* arm64: fix typo in a commentJason Wang2021-08-031-1/+1
* arm64: use a common .arch preamble for inline assemblySami Tolvanen2020-08-281-2/+4
* arm64: tlb: Use the TLBI RANGE feature in arm64Zhenyu Ye2020-07-151-29/+125
* arm64: tlb: don't set the ttl value in flush_tlb_page_nosyncZhenyu Ye2020-07-101-3/+2
* arm64: Shift the __tlbi_level() indentation leftCatalin Marinas2020-07-071-22/+21
* arm64: tlb: Set the TTL field in flush_tlb_rangeZhenyu Ye2020-07-071-6/+8
* arm64: Add tlbi_user_level TLB invalidation helperZhenyu Ye2020-07-071-6/+12
* arm64: Add level-hinted TLB invalidation helperMarc Zyngier2020-07-071-0/+45
* arm64: tlb: Ensure we execute an ISB following walk cache invalidationWill Deacon2019-08-271-0/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-12/+1
* arm64: tlbflush: Ensure start/end of address range are aligned to strideWill Deacon2019-06-121-0/+3
* Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2018-12-261-4/+11
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| * arm64: tlbi: Set MAX_TLBI_OPS to PTRS_PER_PTEWill Deacon2018-11-271-2/+2
| * arm64: mm: Don't wait for completion of TLB invalidation when page agingAlex Van Brunt2018-11-261-2/+9
* | arm64: Add workaround for Cortex-A76 erratum 1286807Catalin Marinas2018-11-291-2/+2
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* arm64: tlb: Rewrite stale comment in asm/tlbflush.hWill Deacon2018-09-111-25/+55
* arm64: tlb: Avoid synchronous TLBIs when freeing page tablesWill Deacon2018-09-111-11/+0
* arm64: tlbflush: Allow stride to be specified for __flush_tlb_range()Will Deacon2018-09-111-6/+9
* arm64: tlb: Justify non-leaf invalidation in flush_tlb_range()Will Deacon2018-09-111-0/+4
* arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()Will Deacon2018-09-111-0/+2
* arm64: tlb: Use last-level invalidation in flush_tlb_kernel_range()Will Deacon2018-09-111-1/+1
* arm64: tlbflush: Introduce __flush_tlb_kernel_pgtableChintan Pandya2018-07-061-0/+7
* arm64: tlbflush: avoid writing RES0 bitsPhilip Elcan2018-03-281-8/+17
* arm64: mm: Invalidate both kernel and user ASIDs when performing TLBIWill Deacon2017-12-111-2/+14
* arm64: Work around Falkor erratum 1009Christopher Covington2017-02-011-3/+15
* arm64: tlbflush.h: add __tlbi() macroMark Rutland2016-09-281-8/+26
* arm64: tlb: remove redundant barrier from __flush_tlb_pgtableWill Deacon2015-10-071-1/+0
* arm64: tlbflush: remove redundant ASID casts to (unsigned long)Will Deacon2015-10-071-5/+4
* arm64: flush: use local TLB and I-cache invalidationWill Deacon2015-10-071-0/+8
* arm64: Use last level TLBI for user pte changesCatalin Marinas2015-07-281-5/+16
* arm64: Clean up __flush_tlb(_kernel)_range functionsCatalin Marinas2015-07-281-26/+21
* arm64: move update_mmu_cache() into asm/pgtable.hWill Deacon2015-07-271-14/+0
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