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* Merge tag 'mm-stable-2023-06-24-19-15' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds2023-06-283-1/+6
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| * arm64: allow kmalloc() caches aligned to the smaller cache_line_size()Catalin Marinas2023-06-201-0/+3
| * cachestat: wire up cachestat for other architecturesNhat Pham2023-06-102-1/+3
* | Merge tag 'docs-arm64-move' of git://git.lwn.net/linuxLinus Torvalds2023-06-282-2/+2
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| * | arm64: Fix dangling references to Documentation/arm64Jonathan Corbet2023-06-212-2/+2
* | | Merge tag 'locking-core-2023-06-27' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-06-275-118/+83
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| * | | locking/atomic: make atomic*_{cmp,}xchg optionalMark Rutland2023-06-051-28/+0
| * | | arch: Remove cmpxchg_doublePeter Zijlstra2023-06-054-125/+0
| * | | percpu: Wire up cmpxchg128Peter Zijlstra2023-06-051-0/+20
| * | | arch: Introduce arch_{,try_}_cmpxchg128{,_local}()Peter Zijlstra2023-06-053-0/+98
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* | | Merge tag 'sched-core-2023-06-27' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds2023-06-272-13/+7
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| * | | arm64/arch_timer: Provide noinstr sched_clock_read() functionsPeter Zijlstra2023-06-051-7/+1
| * | | arm64/io: Always inline all of __raw_{read,write}[bwlq]()Peter Zijlstra2023-06-051-6/+6
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* | | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2023-06-2731-182/+305
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| * \ \ Merge branch 'for-next/feat_s1pie' into for-next/coreCatalin Marinas2023-06-238-35/+143
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| | * | | arm64: add encodings of PIRx_ELx registersJoey Gouly2023-06-062-0/+58
| | * | | arm64: disable EL2 traps for PIEJoey Gouly2023-06-062-3/+12
| | * | | arm64: reorganise PAGE_/PROT_ macrosJoey Gouly2023-06-061-28/+44
| | * | | arm64: add PTE_WRITE to PROT_SECT_NORMALJoey Gouly2023-06-061-1/+1
| | * | | arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGSJoey Gouly2023-06-061-4/+4
| | * | | KVM: arm64: Save/restore PIE registersJoey Gouly2023-06-061-0/+4
| | * | | KVM: arm64: Save/restore TCR2_EL1Joey Gouly2023-06-061-0/+1
| | * | | arm64: cpufeature: add system register ID_AA64MMFR3Joey Gouly2023-06-061-0/+1
| | * | | arm64/sysreg: add PIR*_ELx registersJoey Gouly2023-06-061-0/+19
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| *-----------. \ \ \ Merge branches 'for-next/kpti', 'for-next/missing-proto-warn', 'for-next/iss2...Catalin Marinas2023-06-2327-149/+164
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| | | | | | | | * | arm64: cpufeature: fold cpus_set_cap() into update_cpu_capabilities()Mark Rutland2023-06-071-10/+0
| | | | | | | | * | arm64: alternatives: use cpucap namingMark Rutland2023-06-075-33/+33
| | | | | | | | * | arm64: standardise cpucap bitmap namesMark Rutland2023-06-072-7/+7
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| | | | | | | * | arm64/sysreg: Convert TRBIDR_EL1 register to automatic generationAnshuman Khandual2023-06-141-6/+0
| | | | | | | * | arm64/sysreg: Convert TRBTRG_EL1 register to automatic generationAnshuman Khandual2023-06-141-3/+0
| | | | | | | * | arm64/sysreg: Convert TRBMAR_EL1 register to automatic generationAnshuman Khandual2023-06-141-5/+0
| | | | | | | * | arm64/sysreg: Convert TRBSR_EL1 register to automatic generationAnshuman Khandual2023-06-141-12/+0
| | | | | | | * | arm64/sysreg: Convert TRBBASER_EL1 register to automatic generationAnshuman Khandual2023-06-141-3/+0
| | | | | | | * | arm64/sysreg: Convert TRBPTR_EL1 register to automatic generationAnshuman Khandual2023-06-141-3/+0
| | | | | | | * | arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generationAnshuman Khandual2023-06-141-12/+0
| | | | | | | * | arm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-142-5/+5
| | | | | | | * | arm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-2/+2
| | | | | | | * | arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-6/+4
| | | | | | | * | arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-13/+13
| | | | | | | * | arm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-2/+2
| | | | | | | * | arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-2/+2
| | | | | | | * | arm64/sysreg: Rename TRBLIMITR_EL1 fields per auto-gen tools formatAnshuman Khandual2023-06-141-8/+8
| | | | | | | * | arm64/sysreg: Convert OSECCR_EL1 to automatic generationMark Brown2023-06-061-1/+0
| | | | | | | * | arm64/sysreg: Convert OSDTRTX_EL1 to automatic generationMark Brown2023-06-061-1/+0
| | | | | | | * | arm64/sysreg: Convert OSDTRRX_EL1 to automatic generationMark Brown2023-06-061-1/+0
| | | | | | | * | arm64/sysreg: Convert OSLAR_EL1 to automatic generationMark Brown2023-06-061-3/+0
| | | | | | | * | arm64/sysreg: Standardise naming of bitfield constants in OSL[AS]R_EL1Mark Brown2023-06-062-6/+6
| | | | | | | * | arm64/sysreg: Convert MDSCR_EL1 to automatic register generationMark Brown2023-06-061-1/+0
| | | | | | | * | arm64/sysreg: Convert MDCCINT_EL1 to automatic register generationMark Brown2023-06-061-1/+0
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| | | | | | * | arm64: module: rework module VA range selectionMark Rutland2023-06-061-1/+1
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