summaryrefslogtreecommitdiffstats
path: root/arch/arm64 (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2016-04-063-3/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull KVM fixes from Paolo Bonzini: "Miscellaneous bugfixes. The ARM and s390 fixes are for new regressions from the merge window, others are usual stable material" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: compiler-gcc: disable -ftracer for __noclone functions kvm: x86: make lapic hrtimer pinned s390/mm/kvm: fix mis-merge in gmap handling kvm: set page dirty only if page has been writable KVM: x86: reduce default value of halt_poll_ns parameter KVM: Hyper-V: do not do hypercall userspace exits if SynIC is disabled KVM: x86: Inject pending interrupt even if pending nmi exist arm64: KVM: Register CPU notifiers when the kernel runs at HYP arm64: kvm: 4.6-rc1: Fix VTCR_EL2 VS setting
| * arm64: kvm: 4.6-rc1: Fix VTCR_EL2 VS settingSuzuki K Poulose2016-03-303-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we detect support for 16bit VMID in ID_AA64MMFR1, we set the VTCR_EL2_VS field to 1 to make use of 16bit vmids. But, with commit 3a3604bc5eb4 ("arm64: KVM: Switch to C-based stage2 init") this is broken and we corrupt VTCR_EL2:T0SZ instead of updating the VS field. VTCR_EL2_VS was actually defined to the field shift (19) and not the real value for VS. This patch fixes the issue. Fixes: commit 3a3604bc5eb4 ("arm64: KVM: Switch to C-based stage2 init") Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
* | arm64: defconfig: updates for 4.6Will Deacon2016-03-291-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few defconfig updates got dropped on the floor during the merge window, so I've rounded up the remainder here: * Fix duplicate definition of MMC_BLOCK_MINORS and bump to 32 for msm8916 * CPUFreq support for the Juno platform, using the MHU/SCPI interface * Removal of the default command line, which assumed a console called ttyAMA0 * Bits and pieces for the Hi6220 (96Boards HiKey) Signed-off-by: Will Deacon <will.deacon@arm.com>
* | arm64: perf: Move PMU register related defines to asm/perf_event.hShannon Zhao2016-03-295-123/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/perf_event.h header file and rename them with prefix ARMV8_PMU_. This allows us to get rid of kvm_perf_event.h. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* | arm64: opcodes.h: Add arm big-endian config options before including arm headerJames Morse2016-03-291-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm and arm64 use different config options to specify big endian. This needs taking into account when including code/headers between the two architectures. A case in point is PAN, which uses the __instr_arm() macro to output instructions. The macro comes from opcodes.h, which lives under arch/arm. On a big-endian build the mismatched config options mean the instruction isn't byte swapped correctly, resulting in undefined instruction exceptions during boot: | alternatives: patching kernel code | kdevtmpfs[87]: undefined instruction: pc=ffffffc0004505b4 | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c | Internal error: Oops - undefined instruction: 0 [#1] SMP | Modules linked in: | CPU: 0 PID: 87 Comm: kdevtmpfs Not tainted 4.1.16+ #5 | Hardware name: Hisilicon PhosphorHi1382 EVB (DT) | task: ffffffc336591700 ti: ffffffc3365a4000 task.ti: ffffffc3365a4000 | PC is at dump_instr+0x68/0x100 | LR is at do_undefinstr+0x1d4/0x2a4 | pc : [<ffffffc00076231c>] lr : [<ffffffc0000811d4>] pstate: 604001c5 | sp : ffffffc3365a6450 Cc: <stable@vger.kernel.org> #4.3.x- Reported-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Xuefeng Wang <wxf.wang@hisilicon.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arch, ftrace: for KASAN put hard/soft IRQ entries into separate sectionsAlexander Potapenko2016-03-262-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | KASAN needs to know whether the allocation happens in an IRQ handler. This lets us strip everything below the IRQ entry point to reduce the number of unique stack traces needed to be stored. Move the definition of __irq_entry to <linux/interrupt.h> so that the users don't need to pull in <linux/ftrace.h>. Also introduce the __softirq_entry macro which is similar to __irq_entry, but puts the corresponding functions to the .softirqentry.text section. Signed-off-by: Alexander Potapenko <glider@google.com> Acked-by: Steven Rostedt <rostedt@goodmis.org> Cc: Christoph Lameter <cl@linux.com> Cc: Pekka Enberg <penberg@kernel.org> Cc: David Rientjes <rientjes@google.com> Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com> Cc: Andrey Konovalov <adech.fo@gmail.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com> Cc: Konstantin Serebryany <kcc@google.com> Cc: Dmitry Chernenkov <dmitryc@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'arm64-upstream' of ↵Linus Torvalds2016-03-256-52/+36
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull second set of arm64 updates from Catalin Marinas: - KASLR bug fixes: use callee-saved register, boot-time I-cache maintenance - inv_entry asm macro fix (EL0 check typo) - pr_notice("Virtual kernel memory layout...") splitting - Clean-ups: use p?d_set_huge consistently, allow preemption around copy_to_user_page, remove unused __local_flush_icache_all() * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: mm: allow preemption in copy_to_user_page arm64: consistently use p?d_set_huge arm64: kaslr: use callee saved register to preserve SCTLR across C call arm64: Split pr_notice("Virtual kernel memory layout...") into multiple pr_cont() arm64: drop unused __local_flush_icache_all() arm64: fix KASLR boot-time I-cache maintenance arm64/kernel: fix incorrect EL0 check in inv_entry macro
| * arm64: mm: allow preemption in copy_to_user_pageMark Rutland2016-03-241-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we disable preemption in copy_to_user_page; a behaviour that we inherited from the 32-bit arm code. This was necessary for older cores without broadcast data cache maintenance, and ensured that cache lines were dirtied and cleaned by the same CPU. On these systems dirty cache line migration was not possible, so this was sufficient to guarantee coherency. On contemporary systems, cache coherence protocols permit (dirty) cache lines to migrate between CPUs as a result of speculation, prefetching, and other behaviours. To account for this, in ARMv8 data cache maintenance operations are broadcast and affect all data caches in the domain associated with the VA (i.e. ISH for kernel and user mappings). In __switch_to we ensure that tasks can be safely migrated in the middle of a maintenance sequence, using a dsb(ish) to ensure prior explicit memory accesses are observed and cache maintenance operations are completed before a task can be run on another CPU. Given the above, it is not necessary to disable preemption in copy_to_user_page. This patch removes the preempt_{disable,enable} calls, permitting preemption. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: consistently use p?d_set_hugeMark Rutland2016-03-241-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 324420bf91f60582 ("arm64: add support for ioremap() block mappings") added new p?d_set_huge functions which do the hard work to generate and set a correct block entry. These differ from open-coded huge page creation in the early page table code by explicitly setting the P?D_TYPE_SECT bits (which are implicitly retained by mk_sect_prot() for any valid prot), but are otherwise identical (and cannot fail on arm64). For simplicity and consistency, make use of these in the initial page table creation code. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: kaslr: use callee saved register to preserve SCTLR across C callArd Biesheuvel2016-03-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The KASLR code incorrectly expects the contents of x18 to be preserved across a call into C code, and uses it to stash the contents of SCTLR_EL1 before enabling the MMU. If the MMU needs to be disabled again to create the randomized kernel mapping, x18 is written back to SCTLR_EL1, which is likely to crash the system if x18 has been clobbered by kasan_early_init() or kaslr_early_init(). So use x22 instead, which is not in use so far in head.S Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: Split pr_notice("Virtual kernel memory layout...") into multiple ↵Catalin Marinas2016-03-211-32/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | pr_cont() The printk() implementation has a limit of LOG_LINE_MAX (== 1024 - 32) buffer per call which the arm64 mem_init() breaches when printing the virtual memory layout with CONFIG_KASAN enabled. The result is that the last line is no longer printed. This patch splits the call into a pr_notice() + additional pr_cont() calls. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com>
| * arm64: drop unused __local_flush_icache_all()Kefeng Wang2016-03-211-7/+0
| | | | | | | | | | | | | | | | | | | | After commit 65da0a8e34a8 ("arm64: use non-global mappings for UEFI runtime regions"), nobody use __local_flush_icache_all() anymore, so drop it. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64: fix KASLR boot-time I-cache maintenanceMark Rutland2016-03-211-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f80fb3a3d50843a4 ("arm64: add support for kernel ASLR") missed a DSB necessary to complete I-cache maintenance in the primary boot path, and hence stale instructions may still be present in the I-cache and may be executed until the I-cache maintenance naturally completes. Since commit 8ec41987436d566f ("arm64: mm: ensure patched kernel text is fetched from PoU"), all CPUs invalidate their I-caches after their MMU is enabled. Prior a CPU's MMU having been enabled, arbitrary lines may have been fetched from the PoC into I-caches. We never patch text expected to be executed with the MMU off. Thus, it is unnecessary to perform broadcast I-cache maintenance in the primary boot path. This patch reduces the scope of the I-cache maintenance to the local CPU, and adds the missing DSB with similar scope, matching prior maintenance in the primary boot path. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Ard Biesehvuel <ard.biesheuvel@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * arm64/kernel: fix incorrect EL0 check in inv_entry macroArd Biesheuvel2016-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of macro inv_entry refers to its 'el' argument without the required leading backslash, which results in an undefined symbol 'el' to be passed into the kernel_entry macro rather than the index of the exception level as intended. This undefined symbol strangely enough does not result in build failures, although it is visible in vmlinux: $ nm -n vmlinux |head U el 0000000000000000 A _kernel_flags_le_hi32 0000000000000000 A _kernel_offset_le_hi32 0000000000000000 A _kernel_size_le_hi32 000000000000000a A _kernel_flags_le_lo32 ..... However, it does result in incorrect code being generated for invalid exceptions taken from EL0, since the argument check in kernel_entry assumes EL1 if its argument does not equal '0'. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | Merge tag 'armsoc-dt2' of ↵Linus Torvalds2016-03-253-22/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull more ARM DT changes from Arnd Bergmann: "Here are some final updates for ARM SoC specific dts files: - The i.MX changes were sent relatively late, and had a dependency on the clk tree, so I delayed that a bit. Support for the new i.MX6qp SoC and a couple of new boards is added in this branch. - Uniphier renames a few files to match the final product names that were decided by the company, kudos to the kernel developer(s) for getting support upstream before the product release. Also two boards are added. The patches were posted early enough and nice overall, but we forgot to apply them and decided to give it some more time in linux-next - at91 has two small bug fixes" * tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: dts: at91: sama5d4 Xplained: don't disable hsmci regulator ARM: dts: at91: sama5d3 Xplained: don't disable hsmci regulator ARM: dts: uniphier: add pinmux node for I2C ch4 ARM: dts: uniphier: add @{address} to EEPROM node ARM: dts: uniphier: add PH1-Pro4 Sanji board support ARM: dts: uniphier: add PH1-Pro4 Ace board support ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board ARM: dts: uniphier: add reference clock nodes ARM: dts: uniphier: rework UniPhier System Bus nodes ARM: dts: uniphier: factor out ranges property of support card arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20 ARM: dts: imx53-qsb: Fix gpio button polarity ARM: dts: vfxxx: Add DAC node for Vybrid SoC ARM: dts: imx6q: add missing links between ipu2 and mipi dsi ARM: dts: imx: Add support for Advantech/GE B850v3 ARM: dts: imx: Add support for Advantech/GE B650v3 ARM: dts: imx: Add support for Advantech/GE B450v3 ARM: dts: imx: Add support for Advantech/GE Bx50v3 ARM: dts: imx: Add Advantech BA-16 Qseven module ...
| * | ARM: dts: uniphier: rework UniPhier System Bus nodesMasahiro Yamada2016-03-181-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the review process of the UniPhier System Bus driver (drivers/bus/uniphier.c), the current binding of the System Bus Controller turned out to be no good. In order to make the driver really usable, we have to switch over to the new binding defined by Documentation/devicetree/bindings/bus/uniphier-system-bus.txt. The old binding will be still supported for a while to keep the backward compatibility. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: dts: uniphier: factor out ranges property of support cardMasahiro Yamada2016-03-181-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This property is used in common by several boards. Move it to the common place (uniphier-support-card.dtsi). If necessary, each board can still override the property. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20Masahiro Yamada2016-03-183-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the company's awful projecting, this chip has been renamed to PH1-LD20. It has not been shipped yet, this change would have no impact on our customers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2016-03-241-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "A small set of fixes for the usual ARM/SOC irqchip drivers - A set of fixes for mbigen to handle multiple devices in a hardware module proper - A cleanup for the mbigen config option which was pointlessly user configurable. - A cleanup for tegra replacing open coded functionality by the proper core function The config cleanup touches arch/arm64/Kconfig.platforms to select the irq chip for the related platform" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/mbigen: Make CONFIG_HISILICON_IRQ_MBIGEN a hidden option ARM64: Kconfig: Select mbigen interrupt controller on Hisilicon platform irqchip/mbigen: Handle multiple device nodes in a mbigen module irqchip/mbigen: Adjust DT bindings to handle multiple devices in a module irqchip/tegra: Switch to use irq_domain_free_irqs_common
| * | | ARM64: Kconfig: Select mbigen interrupt controller on Hisilicon platformMaJun2016-03-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a interrupt controller used on some of hisilicon SOCs(660,1610 etc.), mbigen driver should be enabled when CONFIG_ARCH_HISI is enabled. Signed-off-by: Ma Jun <majun258@huawei.com> Cc: mark.rutland@arm.com Cc: jason@lakedaemon.net Cc: marc.zyngier@arm.com Cc: Catalin.Marinas@arm.com Cc: guohanjun@huawei.com Cc: Will.Deacon@arm.com Cc: huxinwei@huawei.com Cc: lizefan@huawei.com Cc: dingtianhong@huawei.com Cc: zhaojunhua@hisilicon.com Cc: liguozhu@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1458723993-21044-2-git-send-email-majun258@huawei.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2016-03-232-1/+11
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull more KVM updates from Paolo Bonzini: "Second round of KVM changes for 4.6: - build fixes for PPC KVM - miscellaneous bugfixes for ARM KVM - cleanup of memory barrier and removal of redundant barriers - x86 fixes: page tracking oops, support for old buggy KVM nested on 4.5 - support for protection keys in guests - lockdep fix - another conversion to simple wait queues and raw spinlocks, backported from PREEMPT_RT" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (27 commits) KVM: page_track: fix access to NULL slot KVM: PPC: do not compile in vfio.o unconditionally kvm, rt: change async pagefault code locking for PREEMPT_RT KVM/PPC: update the comment of memory barrier in the kvmppc_prepare_to_enter() KVM/x86: update the comment of memory barrier in the vcpu_enter_guest() KVM: Replace smp_mb() with smp_load_acquire() in the kvm_flush_remote_tlbs() KVM/x86: Call smp_wmb() before increasing tlbs_dirty KVM: Replace smp_mb() with smp_mb_after_atomic() in the kvm_make_all_cpus_request() KVM/x86: Replace smp_mb() with smp_store_mb/release() in the walk_shadow_page_lockless_begin/end() KVM: Remove redundant smp_mb() in the kvm_mmu_commit_zap_page() KVM, pkeys: expose CPUID/CR4 to guest KVM, pkeys: add pkeys support for permission_fault KVM, pkeys: introduce pkru_mask to cache conditions KVM, pkeys: save/restore PKRU when guest/host switches x86: pkey: introduce write_pkru() for KVM KVM, pkeys: add pkeys support for xsave state KVM, pkeys: disable pkeys for guests in non-paging mode KVM: x86: remove magic number with enum cpuid_leafs KVM: MMU: return page fault error code from permission_fault KVM: fix spin_lock_init order on x86 ...
| * | | | kvm: arm64: Disable compiler instrumentation for hypervisor codeCatalin Marinas2016-03-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent rewrite of the arm64 KVM hypervisor code in C, enabling certain options like KASAN would allow the compiler to generate memory accesses or function calls to addresses not mapped at EL2. This patch disables the compiler instrumentation on the arm64 hypervisor code for gcov-based profiling (GCOV_KERNEL), undefined behaviour sanity checker (UBSAN) and kernel address sanitizer (KASAN). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: <stable@vger.kernel.org> # 4.5+ Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * | | | arm64: KVM: Turn kvm_ksym_ref into a NOP on VHEMarc Zyngier2016-03-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running with VHE, there is no need to translate kernel pointers to the EL2 memory space, since we're already there (and we have a much saner memory map to start with). Unfortunately, kvm_ksym_ref is getting in the way, and the first call into the "hypervisor" section is going to end up in fireworks, since we're now branching into nowhereland. Meh. A potential solution is to test if VHE is engaged or not, and only perform the translation in the negative case. With this in place, VHE is able to run again. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
* | | | | Merge tag 'iommu-updates-v4.6' of ↵Linus Torvalds2016-03-221-0/+81
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU updates from Joerg Roedel: - updates for the Exynos IOMMU driver to make use of default domains and to add support for the SYSMMU v5 - new Mediatek IOMMU driver - support for the ARMv7 short descriptor format in the io-pgtable code - default domain support for the ARM SMMU - couple of other small fixes all over the place * tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (41 commits) iommu/ipmmu-vmsa: Add r8a7795 DT binding iommu/mediatek: Check for NULL instead of IS_ERR() iommu/io-pgtable-armv7s: Fix kmem_cache_alloc() flags iommu/mediatek: Fix handling of of_count_phandle_with_args result iommu/dma: Fix NEED_SG_DMA_LENGTH dependency iommu/mediatek: Mark PM functions as __maybe_unused iommu/mediatek: Select ARM_DMA_USE_IOMMU iommu/exynos: Use proper readl/writel register interface iommu/exynos: Pointers are nto physical addresses dts: mt8173: Add iommu/smi nodes for mt8173 iommu/mediatek: Add mt8173 IOMMU driver memory: mediatek: Add SMI driver dt-bindings: mediatek: Add smi dts binding dt-bindings: iommu: Add binding for mediatek IOMMU iommu/ipmmu-vmsa: Use ARCH_RENESAS iommu/exynos: Support multiple attach_device calls iommu/exynos: Add Maintainers entry for Exynos SYSMMU driver iommu/exynos: Add support for v5 SYSMMU iommu/exynos: Update device tree documentation iommu/exynos: Add support for SYSMMU controller with bogus version reg ...
| | \ \ \ \
| | \ \ \ \
| | \ \ \ \
| | \ \ \ \
| *---. \ \ \ \ Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'arm/mediatek', ↵Joerg Roedel2016-03-211-0/+81
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | 'arm/io-pgtable', 'arm/renesas' and 'core' into next
| | | | * | | | | dts: mt8173: Add iommu/smi nodes for mt8173Yong Wu2016-02-251-0/+81
| | | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the iommu/larbs nodes for mt8173 Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* | | | | | | | Merge tag 'arm64-perf' of ↵Linus Torvalds2016-03-212-22/+105
|\ \ \ \ \ \ \ \ | |_|_|_|/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm[64] perf updates from Will Deacon: "I have another mixed bag of ARM-related perf patches here. It's about 25% CPU and 75% interconnect, but with drivers/bus/ languishing without an obvious maintainer or tree, Olof and I agreed to keep all of these PMU patches together. I suspect a whole load of code from drivers/bus/arm-* can be moved under drivers/perf/, so that's on the radar for the future. Summary: - Initial support for ARMv8.1 CPU PMUs - Support for the CPU PMU in Cavium ThunderX - CPU PMU support for systems running 32-bit Linux in secure mode - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)" * tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits) drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC arm-cci: remove unused variable arm-cci: don't return value from void function arm-cci: make private functions static arm-cci: CoreLink CCI-550 PMU driver arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU arm-cci: CCI-500: Work around PMU counter writes arm-cci: Provide hook for writing to PMU counters arm-cci: Add helper to enable PMU without synchornising counters arm-cci: Add routines to save/restore all counters arm-cci: Get the status of a counter arm-cci: write_counter: Remove redundant check arm-cci: Delay PMU counter writes to pmu::pmu_enable arm-cci: Refactor CCI PMU enable/disable methods arm-cci: Group writes to counter arm-cci: fix handling cpumask_any_but return value arm-cci: simplify sysfs attr handling drivers/perf: arm_pmu: implement CPU_PM notifier arm64: dts: Add Cavium ThunderX specific PMU ...
| * | | | | | | arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LCWill Deacon2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7175f0591eb9 ("arm64: perf: Enable PMCR long cycle counter bit") added initial support for a 64-bit cycle counter enabled using PMCR.LC. Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any attempts to set the enable bit are ignored by armv8pmu_pmcr_write. This patch extends the mask to include the new bit. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | | | | arm64: dts: Add Cavium ThunderX specific PMUJan Glauber2016-02-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a compatible string for the Cavium ThunderX PMU. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | | | | arm64: perf: Extend event mask for ARMv8.1Jan Glauber2016-02-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.1 increases the PMU event number space to 16 bit so increase the EVTYPE mask. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | | | | arm64: perf: Enable PMCR long cycle counter bitJan Glauber2016-02-181-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated. To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before. Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | | | | arm64/perf: Add Cavium ThunderX PMU supportJan Glauber2016-02-181-1/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support PMU events on Caviums ThunderX SOC. ThunderX supports some additional counters compared to the default ARMv8 PMUv3: - branch instructions counter - stall frontend & backend counters - L1 dcache load & store counters - L1 icache counters - iTLB & dTLB counters - L1 dcache & icache prefetch counters Signed-off-by: Jan Glauber <jglauber@cavium.com> [will: capitalisation] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | | | | | arm64: perf: Rename Cortex A57 eventsJan Glauber2016-02-181-14/+14
| | |/ / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implemented Cortex A57 events are strictly-speaking not A57 specific. They are ARM recommended implementation defined events and can be found on other ARMv8 SOCs like Cavium ThunderX too. Therefore rename these events to allow using them in other implementations too. Signed-off-by: Jan Glauber <jglauber@cavium.com> [will: capitalisation and ordering] Signed-off-by: Will Deacon <will.deacon@arm.com>
* | | | | | | Merge branch 'efi-core-for-linus' of ↵Linus Torvalds2016-03-211-0/+1
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull EFI updates from Ingo Molnar: "The main changes are: - Use separate EFI page tables when executing EFI firmware code. This isolates the EFI context from the rest of the kernel, which has security and general robustness advantages. (Matt Fleming) - Run regular UEFI firmware with interrupts enabled. This is already the status quo under other OSs. (Ard Biesheuvel) - Various x86 EFI enhancements, such as the use of non-executable attributes for EFI memory mappings. (Sai Praneeth Prakhya) - Various arm64 UEFI enhancements. (Ard Biesheuvel) - ... various fixes and cleanups. The separate EFI page tables feature got delayed twice already, because it's an intrusive change and we didn't feel confident about it - third time's the charm we hope!" * 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits) x86/mm/pat: Fix boot crash when 1GB pages are not supported by the CPU x86/efi: Only map kernel text for EFI mixed mode x86/efi: Map EFI_MEMORY_{XP,RO} memory region bits to EFI page tables x86/mm/pat: Don't implicitly allow _PAGE_RW in kernel_map_pages_in_pgd() efi/arm*: Perform hardware compatibility check efi/arm64: Check for h/w support before booting a >4 KB granular kernel efi/arm: Check for LPAE support before booting a LPAE kernel efi/arm-init: Use read-only early mappings efi/efistub: Prevent __init annotations from being used arm64/vmlinux.lds.S: Handle .init.rodata.xxx and .init.bss sections efi/arm64: Drop __init annotation from handle_kernel_image() x86/mm/pat: Use _PAGE_GLOBAL bit for EFI page table mappings efi/runtime-wrappers: Run UEFI Runtime Services with interrupts enabled efi: Reformat GUID tables to follow the format in UEFI spec efi: Add Persistent Memory type name efi: Add NV memory attribute x86/efi: Show actual ending addresses in efi_print_memmap x86/efi/bgrt: Don't ignore the BGRT if the 'valid' bit is 0 efivars: Use to_efivar_entry efi: Runtime-wrapper: Get rid of the rtc_lock spinlock ...
| * | | | | | | arm64/vmlinux.lds.S: Handle .init.rodata.xxx and .init.bss sectionsArd Biesheuvel2016-02-221-0/+1
| | |_|/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EFI stub is typically built into the decompressor (x86, ARM) so none of its symbols are annotated as __init. However, on arm64, the stub is linked into the kernel proper, and the code is __init annotated at the section level by prepending all names of SHF_ALLOC sections with '.init'. This results in section names like .init.rodata.str1.8 (for string literals) and .init.bss (which is tiny), both of which can be moved into the .init.data output section. Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/1455712566-16727-6-git-send-email-matt@codeblueprint.co.uk Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | | | | | | Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-03-2062-193/+4115
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "The arm64 device tree changes make up an increasing portion of the overall changes, so they are kept separate from the 32-bit devicetree changes and from the other arm64 updates. Newly added SoCs and boards are: - 96Boards Husky board - AMD Overdrive board - Amlogic S905 SoC and related Tronsmart boxes - Annapurna Labs Alpine family and development board - Broadcom Vulcan servers - Broadcom Northstar 2 SoC - Marvell Armada 3700 family and development board - Qualcomm MSM8996 SoC Additional devices are enabled for existing platforms from Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a couple of other updates for Rockchip, Xilinx and NXP/Freescale" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits) ARM64: dts: amlogic: Add Tronsmart Vega S95 configs Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards ARM64: dts: Prepare configs for Amlogic Meson GXBaby Documentation: devicetree: amlogic: Document Meson GXBaby devicetree: bindings: Add vendor prefix for Tronsmart arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi arm64: dts: add the Alpine v2 EVP arm64: dts: marvell: re-order Device Tree nodes for Armada AP806 arm64: dts: marvell: update Armada AP806 clock description arm64: dts: marvell: add Device Tree files for Armada 7K/8K arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform. arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver arm64: dts: apm: mailbox device tree node for APM X-Gene platform. arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2 ...
| * \ \ \ \ \ \ Merge tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson ↵Olof Johansson2016-03-137-0/+411
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt64 This series adds initial support for the Amlogic S905 based Tronsmart Vega S95 Pro, Meta and Telos TV boxes. - Add new DTS to enable support for the boards - Add documentation for compatibles and vendor prefix * tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson: ARM64: dts: amlogic: Add Tronsmart Vega S95 configs Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards ARM64: dts: Prepare configs for Amlogic Meson GXBaby Documentation: devicetree: amlogic: Document Meson GXBaby devicetree: bindings: Add vendor prefix for Tronsmart Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | ARM64: dts: amlogic: Add Tronsmart Vega S95 configsAndreas Färber2016-03-075-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Device Trees for Tronsmart Vega S95 Pro, Meta and Telos TV boxes. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Carlo Caione <carlo@endlessm.com>
| | * | | | | | | ARM64: dts: Prepare configs for Amlogic Meson GXBabyAndreas Färber2016-03-073-0/+187
| | | |_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Carlo Caione <carlo@endlessm.com>
| * | | | | | | Merge tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2016-03-139-0/+701
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt64 mvebu dt64 for 4.6 (part 2) Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board * tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: re-order Device Tree nodes for Armada AP806 arm64: dts: marvell: update Armada AP806 clock description arm64: dts: marvell: add Device Tree files for Armada 7K/8K Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | arm64: dts: marvell: re-order Device Tree nodes for Armada AP806Thomas Petazzoni2016-02-261-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT nodes representing the XOR engines were not placed at the proper location to comply with the requirement of ordering DT nodes by their unit address. This commit fixes this mistake. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | | | | arm64: dts: marvell: update Armada AP806 clock descriptionThomas Petazzoni2016-02-261-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the review from the DT maintainers, the DT binding for the clocks has changed, and we now use a DFX server node exposing a syscon, with the clock nodes being subnodes of the DFX server node. This commit therefore updates the AP806 Device Tree file to use this new DT binding. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| | * | | | | | | arm64: dts: marvell: add Device Tree files for Armada 7K/8KThomas Petazzoni2016-02-269-0/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board. The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of: - An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040). - One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces. In order to represent this from a Device Tree point of view, this commit creates the following hierarchy: * armada-ap806.dtsi - definitions common to dual/quad ap806 * armada-ap806-dual.dtsi - description of the two CPUs * armada-7020.dtsi - description of the 7020 SoC * armada-8020.dtsi - description of the 8020 SoC * armada-ap806-quad.dtsi - description of the four CPUs * armada-7040.dtsi - description of the 7040 SoC * armada-7040-db.dts - description of the 7040 board * armada-8040.dtsi - description of the 8040 SoC The CP110 blocks are not described yet, and will be part of future patch series. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * | | | | | | | Merge tag 'imx-dt64-4.6' of ↵Arnd Bergmann2016-03-022-0/+5
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Merge "NXP/Freescale arm64 dts update for 4.6" from Shawn Guo: - Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116, which affects NXP/Freescale arm64 SoCs LS1043A and LS2080A. * tag 'imx-dt64-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls1043a: Add quirk for Erratum A009116 arm64: dts: ls2080a: Add quirk for Erratum A009116
| | * | | | | | | | arm64: dts: ls1043a: Add quirk for Erratum A009116Rajesh Bhagat2016-02-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | | | | | arm64: dts: ls2080a: Add quirk for Erratum A009116Lijun Pan2016-02-141-0/+2
| | | |_|_|/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | | | | | | Merge tag 'qcom-arm64-for-4.6' of ↵Arnd Bergmann2016-03-0213-23/+880
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Merge "Qualcomm ARM64 Updates for v4.6" from Andy Gross: * Add MSM8996 support * Cleanups for MSM8916 * Updates for APQ8016 SBC * Fixup pmic reg properties * Add RPMCC node for 8916 * Add LPASS audio nodes * Add USB support on MSM8916 * tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (24 commits) arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: qcom: fix usb digital voltage levels arm64: dts: qcom: apq8016-sbc: enable lpass on DB410c arm64: dts: qcom: add lpass node arm64: dts: qcom: add audio pinctrls arm64: dts: qcom: apq8016-sbc: add usb support arm64: dts: qcom: add manual pullup setting to otg. arm64: dts: qcom: msm8916: Add RPMCC DT node ARM64: dts: qcom: Remove size elements from pmic reg properties arm64: dts: msm8996: Add #power-domain-cells property arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhc arm64: dts: apq8016-sbc: move sdhci node under soc node arm64: dts: apq8016-sbc: make 1.8v available on LS expansion arm64: dts: apq8016-sbc: add regulators support arm64: dts: qcom: add lable for smd rpm regulators arm64: dts: remove s2 regulator from smd regulators. arm64: dts: qcom: add correct drive strenght on cs pins arm64: dts: qcom: remove redundant spi cs pins from pinconf arm64: dts: apq8016-sbc: Add aliases to spi device. arm64: dts: Add L2 cache node to msm8916 ...
| | * | | | | | | | arm64: dts: qcom: Fix MPP's function used for LED controlIvan T. Ivanov2016-02-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qcom-spmi-mpp driver is now using string "digital" to denote old "normal" functionality. Update DTS file. Also update the powersource. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
| | * | | | | | | | arm64: dts: qcom: fix usb digital voltage levelsSrinivas Kandagatla2016-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the digital voltage levels from corner values to microvolts as we are going to use s1 regulator directly for vddcx instead of s1_corner. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
| | * | | | | | | | arm64: dts: qcom: apq8016-sbc: enable lpass on DB410cSrinivas Kandagatla2016-02-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the lpass on DB410C. LPASS is used as cpu dai for both analog and digital audio. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>