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* Merge tag 'tegra-for-5.2-arm64-dt-fixes' of ↵Olof Johansson2019-05-162-2/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/late arm64: tegra: Device tree fixes for v5.2-rc1 This contains one patch to disable the recently added XUSB support on Jetson TX2 which is reported to cause boot and CPU hotplug failures in some cases and doesn't allow the core power rail to be switched off. Furthermore there are some changes to enable IOMMU support on more devices. This is needed in order to prevent these devices from breaking with the policy change in the ARM SMMU driver to break insecure devices that is currently headed for v5.2. * tag 'tegra-for-5.2-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Disable XUSB support on Jetson TX2 arm64: tegra: Enable SMMU translation for PCI on Tegra186 arm64: tegra: Fix insecure SMMU users for Tegra186 Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: tegra: Disable XUSB support on Jetson TX2Thierry Reding2019-05-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recently introduced XUSB support for Jetson TX2 is causing boot, CPU hotplug and suspend/resume failures according to several reports. Temporarily work around this by disabling the XUSB controller and XUSB pad controller nodes in device tree, while we figure out what's causing this. Reported-by: Bitan Biswas <bbiswas@nvidia.com> Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * arm64: tegra: Enable SMMU translation for PCI on Tegra186Thierry Reding2019-05-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") intentionally breaks all devices using the SMMU in bypass mode. This breaks, among other things, PCI support on Tegra186. Fix this by populating the iommus property and friends for the PCIe controller. Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") Signed-off-by: Thierry Reding <treding@nvidia.com>
| * arm64: tegra: Fix insecure SMMU users for Tegra186Jonathan Hunter2019-05-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Commit 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") intentionally breaks all devices using the SMMU in bypass mode. This is breaking various devices on Tegra186 which include the ethernet, BPMP and HDA device. Fix this by populating the iommus property for these devices with their stream ID. Fixes: 954a03be033c ("iommu/arm-smmu: Break insecure users by disabling bypass by default") Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'tegra-for-5.2-arm64-soc-fixes' of ↵Olof Johansson2019-05-161-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/late arm64: tegra: Core fixes for v5.2-rc1 This enables the ARM_GIC_PM driver by default for Tegra in order to increase build coverage. * tag 'tegra-for-5.2-arm64-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Select ARM_GIC_PM Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: tegra: Select ARM_GIC_PMSameer Pujar2019-05-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ARM_GIC_PM for 64-bit Tegra devices. This is required to ensure that the driver gets built into kernel and helps to register the AGIC device when enabled in DT. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | Merge tag 'armsoc-defconfig' of ↵Linus Torvalds2019-05-161-44/+56
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC defconfig updates from Olof Johansson: "Mostly the usual churn due to options being reordered or not added in the right locations. Some various enabling of new drivers, etc. ... i.e. the usual updates, nothing particularly sticks out" * tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (23 commits) arm64: defconfig: Update UFSHCD for Hi3660 soc ARM: multi_v7_defconfig: Enable support for STPMIC1 ARM: multi_v7_defconfig: Enable missing drivers for supported Chromebooks arm64: defconfig: enable mv-xor driver ARM: Enable Trusted Foundations for multiplatform ARM v7 ARM: tegra: Enable Trusted Foundations by default ARM: tegra: Update default configuration for v5.1-rc1 ARM: multi_v7_defconfig: Update for moved options ARM: multi_v7_defconfig: Update for dropped options ARM: shmobile: Enable USB [EO]HCI HCD PLATFORM support in shmobile_defconfig ARM: shmobile: Enable PHY_RCAR_GEN3_USB2 in shmobile_defconfig ARM: qcom_defconfig: add options for LG Nexus 5 phone arm64: defconfig: include the Agilex platform to the arm64 defconfig arm64: defconfig: Add PWM Fan support arm64: defconfig: Enable Tegra HDA support ARM: multi_v7_defconfig: Enable support for CFI NOR FLASH ARM: shmobile: defconfig: Enable support for CFI NOR FLASH ARM: shmobile: defconfig: Refresh for v5.1-rc1 ARM: multi_v7_defconfig: enable the Amlogic Meson ADC and eFuse drivers arm64: defconfig: enable fpga and service layer ...
| * \ \ Merge tag 'mvebu-arm64-5.2-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2019-04-291-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm/defconfig mvebu arm64 for 5.2 (part 1) - Update the defconfig to enable the mv-xor driver found on the Armada 3700 * tag 'mvebu-arm64-5.2-1' of git://git.infradead.org/linux-mvebu: arm64: defconfig: enable mv-xor driver Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | arm64: defconfig: enable mv-xor driverThomas Petazzoni2019-04-211-0/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv-xor DMA driver is used for the XOR engine found in the ARM64 Marvell Armada 3720 SoC, so it makes sense to have it enabled in the arm64 defconfig. A recent boot-time regression was found in mv-xor, which would have been more easily noticed with this driver enabled by default. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: John David Anglin <dave.anglin@bell.net> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| * | | Merge tag 'renesas-arm64-defconfig-for-v5.2' of ↵Olof Johansson2019-04-291-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/defconfig Renesas ARM64 Based SoC Defconfig Updates for v5.2 + Enable support for RX-8571/RX-8581 RTC * tag 'renesas-arm64-defconfig-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: defconfig: enable RX-8581 config option Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | arm64: defconfig: enable RX-8581 config optionBiju Das2019-03-181-0/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for RX-8571/RX-8581 RTC by turning on CONFIG_RTC_DRV_RX8581 as module. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | Merge tag 'sunxi-config64-for-5.2' of ↵Olof Johansson2019-04-291-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig Allwinner arm64 defconfig changes for 5.2 Just a single patch to enable our SPI controller on the arm64 defconfig. * tag 'sunxi-config64-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: defconfig: Enable SPI_SUN6I Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | arm64: defconfig: Enable SPI_SUN6IJagan Teki2019-03-181-0/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SUN6I SPI controller for Allwinner ARM64 SoC's. This would helpful to setup spi flash, for another booting source. mark it as static since it require during boot. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * | | Merge tag 'tegra-for-5.2-arm64-defconfig' of ↵Olof Johansson2019-04-291-0/+3
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/defconfig arm64: tegra: Default configuration updates for v5.2-rc1 These patches enable PWM fan and Tegra HDA support in the 64-bit ARM default configuration, so that these features are enabled by default. * tag 'tegra-for-5.2-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: defconfig: Add PWM Fan support arm64: defconfig: Enable Tegra HDA support Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | arm64: defconfig: Add PWM Fan supportJon Hunter2019-04-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra194 Jetson AGX Xavier board includes a PWM based fan. Enable PWM fan support in the ARM64 defconfig to support the fan on this board. Please note that the device-tree PWM fan node is already present for this board. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | arm64: defconfig: Enable Tegra HDA supportJon Hunter2019-04-031-0/+2
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for Tegra HDA controller in the ARM64 defconfig which is used by Tegra210, Tegra186 and Tegra194. Please note that the Tegra HDA controller requires the HDA HDMI/DP codec driver and so enable this as well. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | arm64: defconfig: Update UFSHCD for Hi3660 socValentin Schneider2019-04-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7ee7ef24d02d ("scsi: arm64: defconfig: enable configs for Hisilicon ufs") set 'CONFIG_SCSI_UFS_HISI=y', but the configs it depends on (CONFIG_SCSI_HFSHCD_PLATFORM && CONFIG_SCSI_UFSHCD) were left to being built as modules. Commit 1f4fa50dd48f ("arm64: defconfig: Regenerate for v4.20") "fixed" that by reverting to 'CONFIG_SCSI_UFS_HISI=m'. Thing is, if the rootfs is stored in the on-board flash (which is the "canonical" way of doing things), we either need these drivers to be built-in, or we need to fiddle with an initramfs to access that flash and eventually load the modules installed over there. The former is the easiest, do that. Signed-off-by: Valentin Schneider <valentin.schneider@arm.com> Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | Merge tag 'arm64_defconfig_for_v5.2' of ↵Olof Johansson2019-04-291-41/+47
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/defconfig ARM64 defconfig updates for v5.1 - 'make savedefconfig' cleanup - Enable PCIE_ALTERA and PCIE_ALTERA_MSI - Enable the Intel Stratix10 Service layer driver, FPGA manager and Altera Freeze Bridge driver. - Adds the Intel Agilex platform to the arm64 defconfig * tag 'arm64_defconfig_for_v5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: defconfig: include the Agilex platform to the arm64 defconfig arm64: defconfig: enable fpga and service layer arm64: defconfig: enable PCIE_ALTERA Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | arm64: defconfig: include the Agilex platform to the arm64 defconfigDinh Nguyen2019-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Build the Agilex platform in the standard arm64 defconfig. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| | * | | arm64: defconfig: enable fpga and service layerDinh Nguyen2019-03-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable FPGA framework, Intel Stratix10 SoC FPGA manager, Stratix10 service layer, and Altera Freeze Bridge drivers. Intel Stratix10 service layer driver was added with commit 7ca5ce896524 ("firmware: add Intel Stratix10 service layer driver"). Intel Stratix10 service layer provides kernel APIs for drivers to request access to the secure features. Such features include FPGA programming, remote status update, and read and write secure registers. While clients of the service layer can be built as modules, the service layer itself has to be configured as built-in. The service layer is dependent on ARCH_STRATIX10. Enabling Altera Freeze Bridge depends on commit 38cd7ad5bd25 ("fpga: altera_freeze_bridge: remove restriction to socfpga"). Signed-off-by: Richard Gong <richard.gong@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| | * | | arm64: defconfig: enable PCIE_ALTERADinh Nguyen2019-03-281-41/+39
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_PCIE_ALTERA and CONFIG_PCIE_ALTERA_MSI. Also do a make savedefconfig to clean up. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | | | Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-05-16152-879/+11687
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM Device-tree updates from Olof Johansson: "Besides new bindings and additional descriptions of hardware blocks for various SoCs and boards, the main new contents here is: SoCs: - Intel Agilex (SoCFPGA) - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus) New boards: - Allwinner: + RerVision H3-DVK (H3) + Oceanic 5205 5inMFD (H6) + Beelink GS2 (H6) + Orange Pi 3 (H6) - Rockchip: + Orange Pi RK3399 + Nanopi NEO4 + Veyron-Mighty Chromebook variant - Amlogic: + SEI Robotics SEI510 - ST Micro: + stm32mp157a discovery1 + stm32mp157c discovery2 - NXP: + Eckelmann ci4x10 (i.MX6DL) + i.MX8MM EVK (i.MX8MM) + ZII i.MX7 RPU2 (i.MX7) + ZII SPB4 (VF610) + Zii Ultra (i.MX8M) + TQ TQMa7S (i.MX7Solo) + TQ TQMa7D (i.MX7Dual) + Kobo Aura (i.MX50) + Menlosystems M53 (i.MX53)j - Nvidia: + Jetson Nano (Tegra T210)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits) arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge arm64: dts: bitmain: Add pinctrl support for BM1880 SoC arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board arm64: dts: bitmain: Add GPIO support for BM1880 SoC ARM: dts: gemini: Indent DIR-685 partition table dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20 arm64: dts: msm8998: thermal: Fix number of supported sensors arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones arm64: dts: exynos: Move fixed-clocks out of soc arm64: dts: exynos: Move pmu and timer nodes out of soc ARM: dts: s5pv210: Fix camera clock provider on Goni board ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210 ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250 ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250 ARM: dts: exynos: Move pmu and timer nodes out of soc arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64 arm64: dts: db820c: Add sound card support arm64: dts: apq8096-db820c: Add HDMI display support ...
| * \ \ \ Merge tag 'bitmain-soc-5.2' of ↵Olof Johansson2019-04-292-0/+211
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/dt Bitmain SoC changes for v5.2: - Added GPIO support for BM1880 SoC based on Designware APB GPIO controller - Added GPIO line names for Sophon Edge board based on 96Boards CE specification for accessing GPIOs using line names from userspace tools like MRAA. - Added pinctrl node for BM1880 SoC as a child node of sctrl syscon node. - Added pinctrl support to UARTs exposed on the Sophon Edge board. * tag 'bitmain-soc-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain: arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge arm64: dts: bitmain: Add pinctrl support for BM1880 SoC arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board arm64: dts: bitmain: Add GPIO support for BM1880 SoC Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | arm64: dts: bitmain: Add UART pinctrl support for Sophon EdgeManivannan Sadhasivam2019-04-291-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl support for UARTs exposed on the Sophon Edge board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | arm64: dts: bitmain: Add pinctrl support for BM1880 SoCManivannan Sadhasivam2019-04-291-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports pinmuxing and the pinctrl registers are part of the sctrl block. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | arm64: dts: bitmain: Add GPIO Line names for Sophon Edge boardManivannan Sadhasivam2019-04-291-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO line names for Sophon Edge board based on BM1880 SoC from Bitmain. Line names are based on the board schematics as well as the 96Boards Consumer Edition specification v1.0. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | arm64: dts: bitmain: Add GPIO support for BM1880 SoCManivannan Sadhasivam2019-04-291-0/+54
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO controller IP. IP exposes 3 GPIO controllers with a total of 72 pins. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | Merge tag 'imx-dt64-5.2' of ↵Olof Johansson2019-04-2921-13/+2725
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.2: - Add initial i.MX8MM SoC and EVK board support. - Enable OPP table for cpufreq support on i.MX8MQ, i.MX8QXP and i.MX8MM. - A series from Andrey Smirnov to enable PCIe support for i.MX8MQ. - Add TMU (Thermal Management Unit) device on i.MX8MQ for managing thermal of CPU, GPU, and VPU. - Add SDMA and SAI2 devices for i.MX8MQ SoC and enable wm8524 audio support on EVK board. - Add LPUART, OCOTP and GPU devices for i.MX8MQ SoC. - Add initial i.MX8MQ based Zii Ultra board support - Add SCU general IRQ and watchdog support for i.MX8QXP. - Add audio related devices and PMU for LS1028A. - Enable SATA and cpuidle support for LX2160A. - Other small random updates. * tag 'imx-dt64-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits) arm64: dts: lx2160a: add cpu idle support arm64: dts: imx8mq: fix GPU clock frequency arm64: dts: fsl: imx8mq-evk: link regulator to GPU domain arm64: dts: imx8mm: Add cpufreq properties arm64: dts: imx8qxp-mek: Add i2c1 with pca9646 arm64: dts: imx8qxp: enable scu general irq channel arm64: dts: imx8mq: add GPU node arm64: dts: imx: add Zii Ultra board support arm64: dts: imx8mq: fix higher CPU operating point arm64: dts: imx8mq-evk: Enable PCIE0 interface arm64: dts: imx8mq: Add nodes for PCIe IP blocks arm64: dts: imx8mq: Combine PCIE power domains arm64: dts: imx8mq: Add a node for SRC IP block arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes arm64: dts: lx2160a: add sata node support arm64: dts: ls1028a: Corrected the SATA ecc address arm64: dts: imx8mq: Change ahb clock for imx8mq arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible string arm64: dts: imx8qxp: add system controller watchdog support ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | arm64: dts: lx2160a: add cpu idle supportRan Wang2019-04-221-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lx2160a supports pw20 which could help save more power during cpu is dile. It needs system firmware support via PSCI. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: fix GPU clock frequencyLucas Stach2019-04-221-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2 of "clk: imx: Refactor entire sccg pll clk" dropped the implicit reparenting of the PLL output from the bypass clock to the real PLL. The commit introducing the GPU node had only been tested against v1 of this patch. Without an explicit reparent to the real PLL the GPU is stuck at the bypass clock rate of 25MHz, serverly hampering performance. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: fsl: imx8mq-evk: link regulator to GPU domainLucas Stach2019-04-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Link the SW1AB regulator to the GPU domain, so that it gets enabled when needed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mm: Add cpufreq propertiesLeonard Crestez2019-04-221-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is very similar to imx8mq cpufreq-dt support. Operating points are from datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf Higher opps were omitted (just like imx8mq) because it requires checking speed grade from OCOTP fuses. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8qxp-mek: Add i2c1 with pca9646Leonard Crestez2019-04-221-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an initial description of the i2c1 bus with a pca9646 i2c switch and various gpio expanders and sensors behind that. Only add the sensors which already have upstream drivers. According to the datasheet the pca9646 is software compatible with pca9546 so no driver changes should be required. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8qxp: enable scu general irq channelAnson Huang2019-04-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: add GPU nodeLucas Stach2019-04-221-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the Vivante GC7000L GPU on the i.MX8MQ SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Guido Günther <agx@sigxcpu.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx: add Zii Ultra board supportLucas Stach2019-04-224-0/+846
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Zii Ultra design, also known as RDU3, is the i.MX8M based successor to the the i.MX6 based RDU2. This adds the basic board support for all components which are supported by the upstream kernel at this time. The board comes in 2 different versions, called RMB3 and Zest, which are derived from the same design, but have different layouts and a few small differences in the populated components. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: fix higher CPU operating pointLucas Stach2019-04-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet both industrial and consumer variants support at least 1.3GHz CPU frequency at 1.0V. Only the OPP at 1.5GHz is unavailable on some SKUs and thus need further fuse reading support. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq-evk: Enable PCIE0 interfaceAndrey Smirnov2019-04-111-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Add nodes for PCIe IP blocksAndrey Smirnov2019-04-111-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nodes for two PCIe controllers found on i.MX8MQ. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Combine PCIE power domainsAndrey Smirnov2019-04-111-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to NXP's FAE feedback and a comment in ATF firmware, PCIE1 and PCIE2 power domains can't really be used independently. Due to shared reset line both power domains have to be turned on at the same time. Account for that quirk by combining PCIE power domains into a single 'pgc_pcie' power domain. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Add a node for SRC IP blockAndrey Smirnov2019-04-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a node for reset controller IP block found on i.MX8MQ. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatibleAndrey Smirnov2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark iomuxc_gpr as compatible with "fsl,imx6q-iomuxc-gpr" in order for to allow i.MX6 PCIe driver to use it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodesDaniel Baluta2019-04-111-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in iMX8 QXP RM [1] This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP internal tree. [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf Signed-off-by: Teo Hall <teo.hall@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: lx2160a: add sata node supportPeng Ma2019-04-113-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SATA device nodes for fsl-lx2160a and enable support for QDS and RDB boards. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: ls1028a: Corrected the SATA ecc addressPeng Ma2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the address. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Change ahb clock for imx8mqAngus Ainslie (Purism)2019-04-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set ahb clock on sdma1 to get rid of "Timeout waiting for CH0" on the imx8mq. Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Fix the fsl,imx8mq-sdma compatible stringAngus Ainslie (Purism)2019-04-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo in the compatible string Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8qxp: add system controller watchdog supportAnson Huang2019-04-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8QXP system controller watchdog support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx8mq: Move thermal-zones out of bus nodeFabio Estevam2019-03-291-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | thermal-zones node does not have any register properties and thus shouldn't be placed inside the bus. Move thermal-zones node from soc node to root node in order to fix the following build warning with W=1: arch/arm64/boot/dts/freescale/imx8mq.dtsi:305.18-364.6: Warning (simple_bus_reg): /soc@0/bus@30000000/thermal-zones: missing or empty reg/ranges property Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * | | | arm64: dts: imx: Add i.mx8mm evk basic dts supportJacky Bai2019-03-262-0/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic dts support for i.MM8MM LPDDR4 EVK. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>