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* arm: omap: irq: call set_handle_irq() from .init_irqFelipe Balbi2014-09-111-0/+3
| | | | | | | | | the idea is that board-files won't need to set .handle_irq on their machine_descs, which lets us drop a little more pointless code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: move some more code aroundFelipe Balbi2014-09-111-15/+15
| | | | | | | | | | We want .init_irq to call set_irq_handle() for legacy platforms. Note that this code will also be dropped once omap2/3 devices are completely moved to DT. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: boot: dts: omap2/3/am33xx: drop ti,intc-sizeFelipe Balbi2014-09-113-3/+0
| | | | | | | | | we are now infering number of IRQ lines based on correct compatible flag, which renders this binding completely useless. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: drop ti,intc-size supportFelipe Balbi2014-09-111-3/+0
| | | | | | | | we don't need that anymore since specific devices are passing correct compatible flags. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: boot: dts: am33xx/omap3: fix intc compatible flagFelipe Balbi2014-09-112-2/+2
| | | | | | | | that way, our intc driver can figure out how many IRQ lines INTC has. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: use compatible flag to figure out number of IRQ linesFelipe Balbi2014-09-111-0/+3
| | | | | | | | so far, only am33xx has 128 lines, all other devices have only 96. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: add specific compatibles for omap3 and am33xx devicesFelipe Balbi2014-09-111-1/+3
| | | | | | | | | with this, we can use a compatible flag to figure out how many irq lines are wired up, no need for our TI-specific ti,intc-size binding. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: drop .handle_irq and .init_irq fieldsFelipe Balbi2014-09-113-20/+0
| | | | | | | | | | now we can safely drop those fields from our machine_desc. While at that, also drop the now unused omap_intc_of_init() definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: use IRQCHIP_DECLARE macroFelipe Balbi2014-09-111-5/+3
| | | | | | | | | | | | | IRQCHIP_DECLARE macro is used to declare the same of_device_id structure for irqchips, it's just a helper. No functional changes. Note that we're temporarily including irqchip.h with its full path, until we move this driver to drivers/irqchip/. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: call set_handle_irq() from intc_of_initFelipe Balbi2014-09-111-0/+2
| | | | | | | | this will let us drop .handle_irq and .init_irq fields from our generic machine_descs. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: make intc_of_init staticFelipe Balbi2014-09-112-11/+1
| | | | | | | | nobody uses that function outside of this file, so we don't need to expose it. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: reorganize code a little bitFelipe Balbi2014-09-111-67/+66
| | | | | | | no functional changes, just moving code around. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: always define omap3 supportFelipe Balbi2014-09-111-2/+0
| | | | | | | | remove ifdef around omap3 INTC support. This will make it easier to reuse code for PM. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: rename omap3_intc_regsFelipe Balbi2014-09-111-2/+2
| | | | | | | | just to make it clearer that it can be used on all omaps. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: remove unnecessary base_addr argumentFelipe Balbi2014-09-111-7/+3
| | | | | | | | | omap_intc_handle_irq now had an unnecessary base_addr argument. Let's remove it and fix all callers. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: switch over to intc_readl on omap_intc_handle_irqFelipe Balbi2014-09-111-6/+8
| | | | | | | | | | | an almost blind conversion from readl_relaxed to our newly introduced intc_readl(). While at that, also remove some hardcoded register addresses. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: remove unused macroFelipe Balbi2014-09-111-2/+0
| | | | | | | no functional changes. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: remove rest of irq_banks usageFelipe Balbi2014-09-111-81/+47
| | | | | | | | now we can finally remove the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: add a global omap_nr_irqs variableFelipe Balbi2014-09-111-0/+3
| | | | | | | | this will cache number of irqs. Also in preparation for removal of irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: start to remove irq_banks arrayFelipe Balbi2014-09-111-37/+27
| | | | | | | | | | We have a single bank in that array, this patch is in preparation to remove that array. It just shifts everything to a new set of functions for register IO while also removing old ones. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: define INTC_ILR0 registerFelipe Balbi2014-09-111-0/+1
| | | | | | | | this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* arm: omap: irq: make omap_irq_base globalFelipe Balbi2014-09-111-1/+1
| | | | | | | | This is in preparation for removing the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-for-v3.18/fixes-not-urgent' into omap-for-v3.18/intc-v2Tony Lindgren2014-09-117-21/+21
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| * ARM: OMAP2+: make of_device_ids constUwe Kleine-König2014-09-117-9/+9
| | | | | | | | | | | | | | | | | | | | of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const function parameters and structs for OMAP2+ as const, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: omap2: make arrays containing machine compatible strings constUwe Kleine-König2014-09-111-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition static const char *omap3_boards_compat[] __initconst = { defines a changable array of constant strings. That is you must not do: *omap3_boards_compat[0] = 'f'; but omap3_boards_compat[0] = "another string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: dts: OMAP3+: Add PRM interruptNishanth Menon2014-09-094-0/+4
| | | | | | | | | | | | | | | | | | Provide OMAP3, 4 and OMAP5 with interrupt number for PRM And for DRA7, provide crossbar number for prm interrupt. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: omap: Remove stray ARCH_HAS_OPP referencesMark Brown2014-09-091-5/+0
| | | | | | | | | | | | | | | | | | | | OPP is now a normal kernel library selected by its users rather than a feature that architectures need to enable so ARCH_HAS_OPP serves no function any more - remove the selects. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: DRA7: Add hook in SoC initcalls to enable pm initializationRajendra Nayak2014-09-092-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | With consolidated code, now we can add the required hooks for DRA7 to enable power management. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: minor modifications] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'pull/v3.18/for-omap-soc' of ↵Tony Lindgren2014-09-0913-64/+275
|\ \ | |/ |/| | | https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
| * ARM: OMAP5: Add hook in SoC initcalls to enable pm initializationSantosh Shilimkar2014-09-082-1/+4
| | | | | | | | | | | | | | | | | | | | | | With consolidated code, now we can add the required hooks for OMAP5 to enable power management. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor rebase updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: Enable CPU RET on suspendRajendra Nayak2014-09-084-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplugSantosh Shilimkar2014-09-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug logic. On OMAP5, DRA7, we do not need this in place yet, also, currently the CPU startup pointer is located in omap4_cpu_pm_info instead of cpu_pm_ops. So, isolate the function to hotplug_restart pointer in cpu_pm_ops where it should have belonged, initalize them as per valid startup pointers for OMAP4430/60 as in current logic, however provide dummy_cpu_resume to be the startup location as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: split this out of original code and isolate it] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Avoid all SAR savesRajendra Nayak2014-09-081-21/+34
| | | | | | | | | | | | | | | | | | | | | | | | Get rid of all assumptions about always having a sar base on *all* OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at this point for OMAP5 either. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: Split and optimize] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomainsSantosh Shilimkar2014-09-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the standard power-management technique, the OMAP5 / DRA7 MPU subsystem also employs an SR3-APG (mercury) power management technology to reduce leakage. It allows for full logic and memories retention on MPU_C0 and MPU_C1 and is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the OMAP5 and DRA7 family of processors. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor consolidation] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by defaultSantosh Shilimkar2014-09-083-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables MPUSS ES2 power management mode using ES2_PM_MODE in AMBA_IF_MODE register. 0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together. Broken! Fortunately, we do not support this anymore. 0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode independently. This is one time settings thanks to always ON domain. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: minor conflict resolutions, consolidation for DRA7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependencySantosh Shilimkar2014-09-081-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With EMIF clock-domain put under hardware supervised control, memory corruption and untraceable crashes are observed on OMAP5. Further investigation revealed that there is a weakness in the PRCM on this specific dynamic depedency. The recommendation is to set MPUSS static dependency towards EMIF clock-domain to avoid issues. This recommendation holds good for DRA7 family of devices as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: conflict resolution, dra7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: OMAP5 / DRA7: PM: Update CPU context register offsetSantosh Shilimkar2014-09-081-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same context offset as well. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [rnayak@ti.com: for DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: rebase, split/merge etc..] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
| * ARM: AM437x: use pdata quirks for pinctrl informationKeerthy2014-09-081-0/+3
| | | | | | | | | | | | Provide pdata-quirks for Am437x processor family. Signed-off-by: Keerthy <j-keerthy@ti.com>
| * ARM: DRA7: use pdata quirks for pinctrl informationNishanth Menon2014-09-081-0/+3
| | | | | | | | | | | | Provide pdata-quirks for DRA7 processor family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * ARM: OMAP5: use pdata quirks for pinctrl informationNishanth Menon2014-09-081-0/+4
| | | | | | | | | | | | Provide pdata-quirks for OMAP5 processor family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * ARM: OMAP3+: PRM: register interrupt information from DTNishanth Menon2014-09-081-0/+18
| | | | | | | | | | | | | | | | | | | | Allow the PRM interrupt information to be picked up from device tree. OMAP3 may use legacy boot and needs to be compatible with old dtbs (without interrupt populated), for these, we use the value which is pre-populated. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: Enable wakeup capability for OMAP5, DRA7Nishanth Menon2014-09-081-1/+1
| | | | | | | | | | | | | | | | OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup capability. So, enable the support. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: remove "wkup" eventNishanth Menon2014-09-081-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "wkup" event at bit offset 0 exists only on OMAP3. OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3. The same applies to AM437x as well. Remove the wrong definition. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: PRM: register interrupt information from DTNishanth Menon2014-09-081-0/+40
| | | | | | | | | | | | | | | | | | Allow the PRM interrupt information to be picked up from device tree. the only exception is for OMAP4 which uses values pre-populated and allows compatibility with older dtb. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstractedNishanth Menon2014-09-081-9/+38
| | | | | | | | | | | | | | | | use the generic function to pick up the prm_instance for a generic logic which can be reused from OMAP4+ Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * ARM: OMAP4+: prminst: provide function to find prm_dev instance offsetNishanth Menon2014-09-082-15/+28
| | | | | | | | | | | | | | | | | | | | PRM device instance can vary depending on SoC. We already handle the same during reset of the device, However, this is also needed for other logic instances. So, first abstract this out to a generic function. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | Merge branch 'pull/v3.18/powerdomain-fixes' of ↵Tony Lindgren2014-09-096-16/+106
|\ \ | | | | | | | | | https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
| * | ARM: OMAP4+: PM: Use only valid low power state for CPU hotplugNishanth Menon2014-09-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not all SoCs support OFF mode - for example DRA74/72. So, use valid power state during CPU hotplug. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP4+: PM: use only valid low power state for suspendNishanth Menon2014-09-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are using power domain state as RET and logic state as OFF. This state is OSWR. This may not always be supported on ALL power domains. In fact, on certain power domains, this might result in a hang on certain platforms. Instead, depend on powerdomain data to provide accurate information about the supported powerdomain states and use the appropriate function to query and use it as part of suspend path. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | ARM: OMAP4+: PM: Make logic state programmableNishanth Menon2014-09-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the logic state as different for each power domain. This allows us to customize the deepest power state we should target over all for each powerdomain in the follow on patches. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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