summaryrefslogtreecommitdiffstats
path: root/arch/arm (follow)
Commit message (Collapse)AuthorAgeFilesLines
* ARM: dts: uniphier: Add missing reg properties for glue layerKunihiko Hayashi2023-02-095-0/+14
| | | | | | | | | The nodes for glue layers should include "reg" property. Add the property according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: uniphier: Align node names for SoC-dependent controller and PHYs ↵Kunihiko Hayashi2023-02-095-79/+79
| | | | | | | | | | | with bindings The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-2-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'aspeed-6.3-devicetree' of ↵Arnd Bergmann2023-02-099-3/+651
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 6.3 - New machines * Ufispace NCPLite AST2600 BMC * Facebook Greatlakes AST2600 BMC - Updates for ethanolx, bletchley and tyan s8036 * tag 'aspeed-6.3-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: p10bmc: Enable UART2 ARM: dts: aspeed: Add device tree for Ufispace NCPLite BMC dt-bindings: arm: aspeed: document Ufispace NCPLite BMC dt-bindings: vendor-prefixes: Add prefix for Ufi Space arm: dts: aspeed: tyan s8036: Enable kcs interrupts ARM: dts: aspeed: bletchley: Enable wdtrst1 ARM: dts: aspeed: bletchley: Rename flash1 label ARM: dts: aspeed: ethanolx: Add BIOS flash chip ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1 ARM: dts: aspeed: ethanolx: Add label for the master partition ARM: dts: aspeed: ethanolx: Correct EEPROM device name ARM: dts: aspeed: ethanolx: Enable VUART ARM: dts: aspeed: greatlakes: Add Facebook greatlakes (AST2600) BMC dt-bindings: arm: aspeed: add Facebook Greatlakes board Link: https://lore.kernel.org/r/CACPK8XdbffU5yRSZF-zR2xv-+6aJK+hEXP8TOkW=SvS+nNTGxg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: dts: aspeed: p10bmc: Enable UART2Eddie James2023-02-013-0/+12
| | | | | | | | | | | | | | | | The APSS can be accessed over the second uart on these systems. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20230126220842.885965-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: Add device tree for Ufispace NCPLite BMCJordan Chang2023-01-272-0/+361
| | | | | | | | | | | | | | | | | | Add initial version of device tree for Ufispace NCPlite platform which is equipped with AST2600-based BMC. Signed-off-by: Jordan Chang <jordan.chang@ufispace.com> Link: https://lore.kernel.org/r/20230119102102.73414-4-jordan.chang@ufispace.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * arm: dts: aspeed: tyan s8036: Enable kcs interruptsAli El-Haj-Mahmoud2023-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the BIOS is built with kcs interrupts enabled, not enabling interrupts on the BMC results in very poor IPMI performance. The other way around (BIOS with interrupts disabled, BMC with interrupts enabled) doesn't suffer degraded IPMI performance. Enabling interrupts on the BMC covers both scenarios, and should be the default. TESTED: manually verified IPMI performance when BIOS is built with and without KCS interrupts. Signed-off-by: Ali El-Haj-Mahmoud <aaelhaj@google.com> Link: https://lore.kernel.org/r/20230118150030.2079226-1-aaelhaj@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: bletchley: Enable wdtrst1Potin Lai2023-01-231-0/+11
| | | | | | | | | | | | | | | | | | | | Enable WDTRST1 external signal to send a reset pulse to peripherals while BMC reset. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20221226054535.2836110-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: bletchley: Rename flash1 labelPotin Lai2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In OpenBMC phosphor-software-manager uses "alt-bmc" for the secondary flash label. Rename flash1 label to "alt-bmc" to support the dual image feature in OpenBMC. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20221226054535.2836110-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Add BIOS flash chipKonstantin Aladyshev2023-01-231-0/+11
| | | | | | | | | | | | | | | | | | Add a BIOS flash chip to the DTS to open a possibility to reflash the main CPU BIOS from the BMC. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111113934.1176-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1Konstantin Aladyshev2023-01-231-1/+3
| | | | | | | | | | | | | | | | | | BMC UART1 is connected to the P0 CPU UART1. As the connection has CTS and RTS signals, enable these functions on the BMC side. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111115227.1357-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Add label for the master partitionKonstantin Aladyshev2023-01-231-0/+1
| | | | | | | | | | | | | | | | | | Add label "bmc" for the flash master partition. The master partition is required for the firmware update in the OpenBMC ecosystem. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111100105.707-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Correct EEPROM device nameKonstantin Aladyshev2023-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | BMC on the EthanolX board uses 24LC128 EEPROM chip for the configuration settings. The correct compatible string for this chip is "atmel,24c128". Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111113208.964-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: ethanolx: Enable VUARTKonstantin Aladyshev2023-01-231-0/+7
| | | | | | | | | | | | | | | | | | | | Enable Virtual UART (VUART) module. This module provides virtual serial communication capabilities between host CPU and BMC and can be used for the Serial-Over-LAN (SoL) feature implementation. Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20230111121917.1636-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: greatlakes: Add Facebook greatlakes (AST2600) BMCDelphine CC Chiu2023-01-232-0/+242
| | | | | | | | | | | | | | | | | | Add linux device tree entry related to greatlakes specific devices connected to BMC SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com> Link: https://lore.kernel.org/r/20221111034828.2377-3-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* | Merge tag 'socfpga_dts_updates_for_v6.3' of ↵Arnd Bergmann2023-02-063-6/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA dts updates for v6.3 - Align UART node with bindings - Add pinctrl properties for Stratix10/Agilex - Change address-cells to 2 to support 64-bit address for fpga region * tag 'socfpga_dts_updates_for_v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: socfpga: change address-cells to support 64-bit addressing arm64: dts: stratix10: add i2c pins for pinctrl arm64: dts: add pinctrl-single property for Stratix10/Agilex ARM: dts: socfpga: align UART node name with bindings Link: https://lore.kernel.org/r/20230206162425.311593-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: dts: socfpga: align UART node name with bindingsKrzysztof Kozlowski2023-01-233-6/+6
| |/ | | | | | | | | | | | | Bindings expect UART/serial node names to be "serial". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | Merge tag 'mvebu-dt-6.3-1' of ↵Arnd Bergmann2023-02-033-12/+22
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt mvebu dt for 6.3 (part 1) Fix errors reported by dtbs_check on dove boards * tag 'mvebu-dt-6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: ARM: dts: dove.dtsi: Move ethphy to fix schema error Link: https://lore.kernel.org/r/87357oaxs0.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: dts: dove.dtsi: Move ethphy to fix schema errorMichał Grzelak2023-01-313-12/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running 'make dtbs_check' with schema in net/marvell,orion-mdio.yaml gives following warnings: mdio-bus@72004: Unevaluated properties are not allowed ('ethernet-phy' was unexpected) arch/arm/boot/dts/dove-cubox.dtb arch/arm/boot/dts/dove-cubox-es.dtb arch/arm/boot/dts/dove-d2plug.dtb arch/arm/boot/dts/dove-d2plug.dtb arch/arm/boot/dts/dove-dove-db.dtb arch/arm/boot/dts/dove-d3plug.dtb arch/arm/boot/dts/dove-sbc-a510.dtb As every subnode of mdio is expected to have an @X, ethernet-phy subnode in dove.dtsi doesn't have one. Fix these errors by moving ethernet-phy into relevant .dts files with correct @<reg address>. Signed-off-by: Michał Grzelak <mig@semihalf.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* | Merge tag 'stm32-dt-for-v6.3-1' of ↵Arnd Bergmann2023-02-0314-21/+856
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT for v6.3, round 1 Highlights: ---------- - MPU: - ST boards: - Add following peripherals support on stm32mp13: i2s, SAI, SPDIFRX, DFSDM, Timers - Add timers support on stm32mp135f-dk board. - Add decicated BSEC compatible on STM32MP13. - Rename sound card on STM32MP15 DKx. - Fix yaml validation issues. * tag 'stm32-dt-for-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: fix compatible for BSEC on STM32MP13 ARM: dts: stm32: Update part number NVMEM description on stm32mp131 ARM: dts: stm32: Use new media bus type macros ARM: dts: stm32: Fix User button on stm32mp135f-dk ARM: dts: stm32: add timers support on stm32mp135f-dk ARM: dts: stm32: add timer pins muxing for stm32mp135f-dk ARM: dts: stm32: add timers support on stm32mp131 ARM: dts: stm32: add dfsdm node on stm32mp131 ARM: dts: stm32: add spdifrx node on stm32mp131 ARM: dts: stm32: add sai nodes on stm32mp131 ARM: dts: stm32: add i2s nodes on stm32mp131 ARM: dts: stm32: Remove the pins-are-numbered property ARM: dts: stm32: rename sound card on stm32mp15xx-dkx ARM: dts: stm32: remove sai kernel clock on stm32mp15xx-dkx ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1l ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp157c-emstamp-argon ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-som ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-som Link: https://lore.kernel.org/r/3e815504-e85e-cbd3-6e6d-4e5a7aa7469a@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: dts: stm32: fix compatible for BSEC on STM32MP13 Patrick Delaunay2023-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct compatible for stm32mp13 support. The BSEC driver for STM32MP15x is not compatible with STM32MP13x. For example the proprietary's smc STM32_SMC_BSEC is not supported in STM32MP13x OP-TEE, it is replaced by SM32MP BSEC Pseudo Trusted Application in OP-TEE to access to the secured IP BSEC on STM32MP13X SoC. The correct compatible is already used in U-Boot and in upstream is in progress for OP-TEE device tree. As the SoC STM32MP13X is not yet official and it is not available outside STMicroelectronics, it is the good time to break the DTS compatibility and to correct the error done in the introduction of STM32MP131. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Update part number NVMEM description on stm32mp131Patrick Delaunay2023-02-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32MP13x Device Part Number (also named RPN in reference manual) only uses the first 12 bits in OTP4, all the other bit are reserved and they can be different of zero; they must be masked in NVMEM result, so the number of bits must be defined in the nvmem cell description. Fixes: 1da8779c0029 ("ARM: dts: stm32: add STM32MP13 SoCs support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Use new media bus type macrosLaurent Pinchart2023-01-172-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that a header exists with macros for the media interface bus-type values, replace hardcoding numerical constants with the corresponding macros in the DT sources. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Fix User button on stm32mp135f-dkAmelie Delaunay2023-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following dtbs_check warning on stm32mp135f-dk: arch/arm/boot/dts/stm32mp135f-dk.dtb: gpio-keys: 'user-pa13' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/input/gpio-keys.yaml It renames user-pa13 node into button-user so that it matches gpio-keys bindings. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add timers support on stm32mp135f-dkOlivier Moysan2023-01-171-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | Configure timers support on stm32mp135f-dk. The timers TIM3, TIM4, TIM8 & TIM14 which can be used on expansion GPIO connector are disabled by default. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add timer pins muxing for stm32mp135f-dkOlivier Moysan2023-01-171-0/+60
| | | | | | | | | | | | | | | | | | | | | Add timer pins muxing for stm32mp135f-dk board. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add timers support on stm32mp131Olivier Moysan2023-01-171-0/+557
| | | | | | | | | | | | | | | | | | | | | Add timers support to STM32MP13x SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add dfsdm node on stm32mp131Olivier Moysan2023-01-171-0/+30
| | | | | | | | | | | | | | | | | | | | | Add DFSDM peripheral support for the STM32MP13 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add spdifrx node on stm32mp131Olivier Moysan2023-01-171-0/+13
| | | | | | | | | | | | | | | | | | | | | Add S/PDIFRX peripheral support for the STM32MP13 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add sai nodes on stm32mp131Olivier Moysan2023-01-171-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | Add SAI1 and SAI2 peripherals support for the STM32MP13 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Change-Id: I79af484702fa4108c106e6013f82d33638e92e6d Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: add i2s nodes on stm32mp131Olivier Moysan2023-01-171-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Add I2S1, I2S2, I2S3 and I2S4 peripherals support for the STM32MP13 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Remove the pins-are-numbered propertyBernhard Rosenkränzer2023-01-175-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the pins-are-numbered property from STM32 DeviceTrees Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: rename sound card on stm32mp15xx-dkxOlivier Moysan2023-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the sound card for STM32MP15x DK boards to manage SoC diversity management. This typically allows to discriminate the sound cards for STM32MP15 and STM32MP13 SoCs. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: remove sai kernel clock on stm32mp15xx-dkxOlivier Moysan2023-01-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove clocks property in the SAI2A subblock node as this property is already defined in the SoC DT. Keep only this property when the master clock is added in the node. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1lPatrice Chotard2023-01-171-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip select pinctrl phandle was missing in several stm32mp15x based boards. Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Oleksij Rempel <o.rempel@pengutronix.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp157c-emstamp-argonPatrice Chotard2023-01-171-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip select pinctrl phandle was missing in several stm32mp15x based boards. Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Reinhold Mueller <reinhold.mueller@emtrion.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-somPatrice Chotard2023-01-171-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chip select pinctrl phandle was missing in several stm32mp15x based boards. Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
| * | ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-somPatrice Chotard2023-01-171-2/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Chip select pinctrl phandle was missing in several stm32mp15x based boards. Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
* | Merge tag 'v6.3-rockchip-dts32-1' of ↵Arnd Bergmann2023-02-038-0/+2191
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Two new 32bit SoC were added, the rv1126 and rk3128. New boards are thr rk3128-eval-board, and a number of rv1126-based compute modules from Edgeble AI. Also included are some dt-binding improvements with relevant Acks from maintainers when the changes touch these areas. * tag 'v6.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: phy: rename phy-rockchip-inno-usb2.yaml dt-bindings: soc: rockchip: grf: add rockchip,rk3288-dp-phy.yaml dt-bindings: phy: rockchip: convert rockchip-dp-phy.txt to yaml ARM: dts: rockchip: Enable Ethernet on rv1126 Neu2-IO ARM: dts: rockchip: Add Ethernet GMAC node for RV1126 ARM: dts: rockchip: Add ethernet rgmiim1 pin-control for rv1126 dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 6 ARM: dts: rockchip: add brcmf node to rk3066a-mk808 ARM: dts: rockchip: add space between label and nodename nfc pinctrl on rk3128 ARM: dts: rockchip: add rk3128-evb ARM: dts: rockchip: add rk3128 soc dtsi dt-bindings: arm: rockchip: Add Rockchip RK3128 Evaluation board ARM: dts: rockchip: Add Edgeble Neural Compute Module 2(Neu2) IO board ARM: dts: rockchip: Add Edgeble RV1126 Neural Compute Module 2(Neu2) dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd. ARM: dts: rockchip: Add Rockchip RV1126 SoC ARM: dts: rockchip: Add Rockchip RV1126 pinctrl dt-bindings: arm: rockchip: Add pmu compatible for rv1126 Link: https://lore.kernel.org/r/5651506.31r3eYUQgx@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: dts: rockchip: Enable Ethernet on rv1126 Neu2-IOAnand Moon2023-01-151-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip RV1126 has GMAC 10/100/1000M ethernet controller. Enable ethernet node on Neu2-IO board. Co-Developed-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Anand Moon <anand@edgeble.ai> Link: https://lore.kernel.org/r/20230111172437.5295-4-anand@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add Ethernet GMAC node for RV1126Anand Moon2023-01-151-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip RV1126 has GMAC 10/100/1000M ethernet controller Co-Developed-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Anand Moon <anand@edgeble.ai> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20230111172437.5295-3-anand@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add ethernet rgmiim1 pin-control for rv1126Anand Moon2023-01-151-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ethernet pin-control for rv1126 SoC. Co-Developed-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Anand Moon <anand@edgeble.ai> Link: https://lore.kernel.org/r/20230111172437.5295-2-anand@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: add brcmf node to rk3066a-mk808Johan Jonker2023-01-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MK808 board has a wifi chip called RK901. Add a somewhat brcmf compatible node to the rk3066a-mk808.dts file. That's what's available as driver in the mainline kernel in relation to this Rockchip wifi product that is able to load the firmware. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/b3c7f1d7-47fd-90e4-badb-e8ceb8901e27@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: add space between label and nodename nfc pinctrl on rk3128Johan Jonker2023-01-101-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add space between label and nodename nfc pinctrl node. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/67675d28-87c5-0df1-4b93-2f1233918a1e@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: add rk3128-evbJohan Jonker2022-12-262-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | Add rk3128 eval board dts Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/56dbd2ab-dc2c-2f7d-0403-1d29dfd3c2e7@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: add rk3128 soc dtsiJohan Jonker2022-12-261-0/+916
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic rk3128 support. Features: Quad-core ARM Cortex-A7MP Core processor Clock & reset unit Power management unit Interrupt controller DMAC 6x 64 bits Timers 4x PWMs 1x 32 bits watchdog Internal memory: Internal BootRom Internal SRAM 8KB External memory: Dynamic Memory Interface (DDR3/DDR3L/LPDDR2) Nand Flash Interface eMMC Interface SD/MMC Interface Connectivity: SDIO interface SPI Controller 3x UART controller 4x I2C controllers 4x groups of GPIO (GPIO0~GPIO3), 32 GPIOs per group USB Host2.0 USB OTG2.0 Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/b7bac0b3-3c91-1026-d435-6b5e9d6492f3@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add Edgeble Neural Compute Module 2(Neu2) IO boardJagan Teki2022-12-262-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. General features: - microSD slot - MIPI DSI connector - 2x USB Host - 1x USB OTG - Ethernet - mini PCIe - Onboard PoE - RS485, RS232, CAN - Micro Phone array - Speaker - RTC battery slot - 40-pin expansion Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20221129075424.189655-9-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add Edgeble RV1126 Neural Compute Module 2(Neu2)Jagan Teki2022-12-261-0/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. General features: - Rockchip RV1126 - 2/4GB LPDDR4 - 8/16/32GB eMMC - 2x MIPI CSI2 FPC connector - Fn-link 8223A-SR WiFi/BT Industrial grade (-40 °C to +85 °C) version of the same class of module called Neu2k powered with Rockchip RV1126K. Neu2 needs to mount on top of Edgeble IO boards for creating complete platform solutions. Add support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20221129075424.189655-8-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add Rockchip RV1126 SoCJagan Teki2022-12-261-0/+438
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 hybrid operation and computing power is up to 2.0TOPs. This patch add basic core dtsi support. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20221129075424.189655-5-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | ARM: dts: rockchip: Add Rockchip RV1126 pinctrlJagan Teki2022-12-261-0/+211
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl definitions for Rockchip RV1126. From RK3568 on-wards pinctrl configurations are maintained in common conf file rockchip-pinconf.dtsi and it is available in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi). So, include the same conf file to RV1126 pinctrl from arm64 path. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20221129075424.189655-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v6.2-next-dts32' of ↵Arnd Bergmann2023-02-034-5/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt Clean ups only: - deleting unsused pins-are-numbered property - not existing second IRQ * tag 'v6.2-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: ARM: dts: mediatek: Remove pins-are-numbered property arm: dts: mt7629: Remove extra interrupt from timer node Link: https://lore.kernel.org/r/17aee808-1f3f-fe75-68d4-adb71915e5cb@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-22 03:40:39 +0100