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* atmel-mci: Driver for Atmel on-chip MMC controllersHaavard Skinnemoen2008-07-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the MMC controller on the AP7000 chips from Atmel. It should in theory work on AT91 systems too with some tweaking, but since the DMA interface is quite different, it's not entirely clear if it's worth merging this with the at91_mci driver. This driver has been around for a while in BSPs and kernel sources provided by Atmel, but this particular version uses the generic DMA Engine framework (with the slave extensions) instead of an avr32-only DMA controller framework. This driver can also use PIO transfers when no DMA channels are available, and for transfers where using DMA may be difficult or impractical for some reason (e.g. the DMA setup overhead is usually not worth it for very short transfers, and badly aligned buffers or lengths are difficult to handle.) Currently, the driver only support PIO transfers. DMA support has been split out to a separate patch to hopefully make it easier to review. The driver has been tested using mmc-block and ext3fs on several SD, SDHC and MMC+ cards. Reads and writes work fine, with read transfer rates up to 3.5 MiB/s on fast cards with debugging disabled. The driver has also been tested using the mmc_test module on the same cards. All tests except 7, 9, 15 and 17 succeed. The first two are unsupported by all the cards I have, so I don't know if the driver handles this correctly. The last two fail because the hardware flags a Data CRC Error instead of a Data Timeout error. I'm not sure how to deal with that. Documentation for this controller can be found in many data sheets from Atmel, including the AT32AP7000 data sheet which can be found here: http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
* avr32: improve NGW100 I2C/PMBus setupDavid Brownell2008-06-271-0/+22
| | | | | | | | | | | | Basic I2C initialization for the NGW100 board: - Provide empty i2c device table. Daughtercards may add devices, and the ATtiny24 could do stuff too. - Set up EXTINT(3) so the ATtiny24 can interrupt the AP7000. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* avr32: Allow board to define oscillator ratesAlex2008-06-271-0/+7
| | | | | | | | | | | | On our custom board we have other oscillator rates than on atngw100 and atstk100x. Currently these rates are hardcoded in arch/avr32/mach-at32ap/at32ap700x.c. This patch moves them into board specific code. Signed-off-by: Alex Raimondi <raimondi@miromico.ch> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* [AVR32] Add support for AT32AP7001 and AT32AP7002Haavard Skinnemoen2008-01-251-1/+1
| | | | | | | | | These are derivatives of the AT32AP7000 chip, which means that most of the code stays the same. Rename a few files, functions, definitions and config symbols to reflect that they apply to all AP700x chips, and exclude some platform devices from chips where they aren't present. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* [AVR32] ngw100 i2c-gpio tweaksDavid Brownell2007-10-111-4/+9
| | | | | | | | | | | | | Make the NGW100 bitbang i2c use open drain signaling. Also, speed it up, so it's closer to 100 kHz ... the code paths seem to be long enough that the udelay isn't dominating bit times. The peak bit rate I observed was around 125 kHz, but that's with large delays (usually before ACK/NAK) which hold the overall rate down to around 80 kHz (call it 100 usec/byte on average). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* [AVR32] SMC configuration in clock cyclesKristoffer Nyborg Gregertsen2007-10-111-1/+4
| | | | | | | | | | | | | This patch makes the SMC configuration take timings in clock cycles instead of nanoseconds. A function to calculate timings in clock cycles is added. This patch removes the rounding troubles of the previous SMC configuration method. [hskinnemoen@atmel.com: fix atstk1002/atngw100 flash config] Signed-off-by: Kristoffer Nyborg Gregertsen <gregerts@stud.ntnu.no> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* [AVR32] Wire up USBA deviceHaavard Skinnemoen2007-10-111-0/+1
| | | | | | | Implement at32_add_device_usba() and use it to wire up the USBA device on ATSTK1000 and ATNGW100. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* [AVR32] Wire up i2c-gpio on the ATNGW100 boardHaavard Skinnemoen2007-08-151-0/+18
| | | | | | | | The NGW100 has a board controller which is hooked up to the TWI lines on AP7000. Since the TWI driver isn't in mainline, use the i2c-gpio driver in the mean time. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* leds: leds-gpio for ngw100David Brownell2007-07-161-0/+31
| | | | | | | | | Add GPIO leds to the NGW100 platform and its defconfig. Access through /sys/class/leds/{a,b,sys}/* files; one defaults to a heartbeat. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
* [AVR32] NGW100, Remove relics of the old USART mapping schemeben.nizette@iinet.net.au2007-06-231-3/+0
| | | | | | | | | USART mapping used to be accomplished by the manual filling of at32_usart_map[] and at32_nr_usarts. This has now been replaced with at32_map_usart() so we can remove these variables. Signed-off-by: Ben Nizette <ben.nizette@iinet.net.au> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* [AVR32] Board code for ATNGW100Haavard Skinnemoen2007-04-273-0/+220
Add board code and defconfig for the ATNGW100 Network Gateway kit. For more information about this board, see http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102 Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>