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* microblaze: Align comments with register usageMichal Simek2020-01-091-4/+4
| | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Increase max dtb size to 64K from 32KSiva Durga Prasad Paladugu2019-10-251-1/+1
| | | | | | | | This patch increases max dtb size to 64K from 32K. This fixes the issue of kernel hang with larger dtb of size greater than 32KB. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: delete wrong comment about machine_early_initMasahiro Yamada2018-07-301-5/+0
| | | | | | | | machine_early_init is defined in arch/microblaze/kernel/setup.c I do not see mach-* directory for MicroBlaze. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Fix typo in head.S s/substract/subtract/Antonio Ospite2014-06-051-1/+1
| | | | | | | Signed-off-by: Antonio Ospite <ao2@ao2.it> Cc: Michal Simek <monstr@monstr.eu> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Fix a typo when disabling stack protectionEdgar E. Iglesias2014-02-101-1/+1
| | | | | | | | | Correct a typo causing the stack protector to be left enabled. 0xFFFFFFF -> 0xFFFFFFFF Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Disable stack protection from bootloaderMichal Simek2014-01-271-0/+4
| | | | | | | Microblaze without MMU can use stack protection in bootloader and kernel should clear this setting ASAP. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Calculate kernel pad automaticallyMichal Simek2013-11-071-1/+1
| | | | | | | | | | The kernel needs to setup the first two tlbs with pad which is used for early page allocation which is used by mapin_ram() to allocate tables for lowmem memory before memory initialisation is done. Calculate pad directly from lowmem size. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Do not use r6 in head.SMichal Simek2013-05-091-10/+10
| | | | | | | r6 stores pointer to ramdisk and shouldn't be used before it is passed to machine_early_init. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Fix bug with passing command lineMichal Simek2012-10-041-5/+9
| | | | | | | | | | | | | | | When u-boot passes control over to Linux it places the Linux command line between to the end of __init_end. When space between __init_end and __bss_start is not COMMAND_LINE_SIZE then the part of cmdline can be lost. In extreme case if __init_end == __bss_start u-boot can't pass any cmdline to Linux kernel. This patch fix this issue by copying cmd line directly to cmd_line char array which is placed in data section. Reported-by: David Mc Andrew <david.mcandrew@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Handle TLB skip size dynamicallyMichal Simek2012-03-231-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the problem with rootfs on JFFS2 with early printk console turned on. The origin version used TLB63 for temporary early printk mapping. The code expect that kernel is not able to use all 64 TLB entries till early printk console is remapped by ioremap. After that temporary mapping on TLB63 is silently lost. This expectation give the opportunity to have early console pretty early. Microblaze systems with JFFS2 rootfs with early printk console turned on used more than 64 TLB entries before kernel can remap early console. Based on that kernel does access to bad area because early printk mapping is rewritten. This patch introduces tlb_skip variable which dynamically stores number of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1 should be skipped. MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start. They can be used for user purpose. TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID). Also clean TLBLO when kernel starts. For specific kernel sizes kernel can use just one TLB. Detect this case and use the second TLB for general purpose. Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE. Export tlb_skip size through debugfs. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Improve TLB calculation for small systemsMichal Simek2012-03-231-5/+93
| | | | | | | | Systems with small amount of memory need to be handled differently. Linux can't allocate the whole 32MB with two TLBs because then there is no MMU protection. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Extend space for compiled-in FDT to 32kBMichal Simek2012-03-231-1/+1
| | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Clear all MSR flags on the first kernel instructionMichal Simek2012-03-231-3/+2
| | | | | | | | | | The main reason is bug because of dynamic TLB allocation. U-BOOT didn't disable dcache and then writing to physical address from ASM wan't visible for reading through MMU. Disabling caches and clearing all flags from previous code is good to do so. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Do not use "la" pseudo instruction - use addik insteadMichal Simek2011-03-091-6/+6
| | | | | | | "la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Optimize BE/LE bootup detectingMichal Simek2011-03-091-5/+7
| | | | | | | | Save 0x1 word to rodata section and remove online value loading if DTB is passed from bootloader. It saves two asm instructions in bootup. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Fix msr instruction detectionMichal Simek2011-02-071-8/+7
| | | | | | | | | | | Fix msr instructions detection. The current code just use msrclr for loading msr content and compare it with proper MSR content. If msrclr is not implemented r8 contains pc address. Previous code wanted to use MSR carry bit but if msrclr wasn't implemented carry wasn't cleared. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Fix DTB passing from bootloaderMichal Simek2011-01-281-2/+12
| | | | | | | | | | | | | Little endian system needs to check OF_DT_HEADER but it is swapped because it is in big-endian. Microblaze LE provides lwr instruction which loads magic number in BIG endian format which can be compared. There is used the fact that if you write 0x1 as word and load it as byte then you get for big-endian zero and 1 for little-endian. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Allow PAGE_SIZE configurationSteven J. Magnani2010-08-041-2/+2
| | | | | | | | | | Allow developer to configure memory page size at compile time. Larger pages can improve performance on some workloads. Based on PowerPC code. Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Quiet section mismatch warningsSteven J. Magnani2010-05-061-1/+2
| | | | | | | | _start is located in .text, which causes mismatch warnings with machine_early_init() and start_kernel() in .init.text. Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: head.S typo fixMichal Simek2010-04-011-2/+2
| | | | | | I forget to change register name in comments. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Use MICROBLAZE_TLB_SIZE in asm codeMichal Simek2010-04-011-1/+1
| | | | | | | TLB size was hardcoded in asm code. This patch brings ability to change TLB size only in one place. (mmu.h). Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Support systems without lmb bramMichal Simek2010-04-011-0/+6
| | | | | | | | | | | | | | | | | | | | When the system has no lmb bram, main memory should be start from zero because of microblaze vectors. DTS fragment could look like: DDR2_SDRAM: memory@0 { device_type = "memory"; reg = < 0x0 0x10000000 >; } ; Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused that kernel physical start address will be zero. On reset vector place will be jump to 0x100 and on 0x100 starts kernel text. You have to solve how to load the kernel before cpu starts. Tested with XMD. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Change temp register for cmdlineMichal Simek2010-03-111-6/+7
| | | | | | | | | | For copy was used r7 register when CONFIG_CMDLINE_BOOL option is enabled. But r7 stores pointer to fdt that's why machine_early_init not detect compiled-in DTB. I also moved kernel PID setup to have TLB init in one block Signed-off-by: Michal Simek <monstr@monstr.eu>
* of: add common header for flattened device tree representationGrant Likely2009-10-151-1/+1
| | | | | | | | | | | | | Add a common header file for working with the flattened device tree data structure and merge the shared data tags used by Microblaze and PowerPC Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
* microblaze: Improve checking mechanism for MSR instructionMichal Simek2009-09-211-8/+5
| | | | | | | It is more safe to use clear instead of msrset. We save some instructions too. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Add checking mechanism for MSR instructionMichal Simek2009-09-211-2/+15
| | | | | | | It was necessary to use fourth parameter(r8) in early_printk to show messages on console. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Clear print messages for DTB passing via r7Michal Simek2009-07-271-0/+3
| | | | | | | | It is necessary to zeroed r7 when r7 points to bad dtb - this caused that we have correct messages about compiled-in dtb or passing via r7 Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Not to clear r7 after copying DTB to kernelMichal Simek2009-07-271-1/+0
| | | | | | | I can't clear r7 because if I do it I lose information where DTB come from. Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze: Final support for statically linked DTBJohn Williams2009-07-271-4/+11
| | | | | | | | | If r7 is zero at kernel boot, or does not point to a valid DTB, then we fall back to a DTB (assumed to be) linked statically in the kernel, instead of blindly copying bogus cruft into the kernel DTB memory region Signed-off-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze_mmu_v2: MMU update for startup codeMichal Simek2009-05-261-0/+190
| | | | Signed-off-by: Michal Simek <monstr@monstr.eu>
* microblaze_v8: assembler files head.S, entry-nommu.S, syscall_table.SMichal Simek2009-03-271-0/+56
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
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