linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	MIPS: features: Add initial support for Segmentation Control registers	Steven J. Hill	2014-01-22	1	-0/+4
*	MIPS: features: Add initial support for TLBINVF capable cores	Leonid Yegoshin	2014-01-22	1	-0/+3
*	MIPS: cpu-features.h: s/MIPS53/MIPS64/	Maciej W. Rozycki	2013-09-24	1	-1/+1
*	MIPS: Optimize current_cpu_type() for better code.	Ralf Baechle	2013-09-17	1	-6/+0
*	MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.	Ralf Baechle	2013-08-05	1	-0/+2
*	MIPS: Cleanup indentation and whitespace	Tony Wu	2013-07-01	1	-16/+16
*	MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS	David Daney	2013-07-01	1	-1/+5
*	MIPS: Get rid of MIPS I flag and test macros.	Ralf Baechle	2013-07-01	1	-1/+10
*	MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem	Huacai Chen	2013-05-08	1	-0/+3
*	Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...	Ralf Baechle	2013-02-21	1	-0/+7
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\| *	MIPS: Probe for and report hardware virtualization support.	David Daney	2013-02-19	1	-0/+4
\| *	MIPS: Add support for the M14KEc core.	Steven J. Hill	2013-02-17	1	-0/+3
* \|	MIPS: Add printing of ISA version in cpuinfo.	Steven J. Hill	2013-02-15	1	-0/+13
* \|	MIPS: Whitespace cleanup.	Ralf Baechle	2013-02-01	1	-9/+9
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*	MIPS: Add detection of DSP ASE Revision 2.	Steven J. Hill	2012-10-11	1	-0/+4
*	MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)	Al Cooper	2012-10-11	1	-0/+4
*	MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.	Steven J. Hill	2012-09-14	1	-3/+0
*	MIPS: Add base architecture support for RI and XI.	Steven J. Hill	2012-09-13	1	-0/+3
*	MIPS: Update comment for cpu_has_clo_clz	Ralf Baechle	2010-08-05	1	-1/+2
*	MIPS: Implement Read Inhibit/eXecute Inhibit	David Daney	2010-02-27	1	-0/+3
*	MIPS: 64-bit: Detect virtual memory size	Guenter Roeck	2010-02-02	1	-0/+7
*	MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.	David Daney	2009-09-17	1	-0/+3
*	MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.	David Daney	2009-06-17	1	-0/+4
*	MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.	David Daney	2009-06-17	1	-0/+4
*	MIPS: Enable CLO / CLZ instructions via separate CPU property	Ralf Baechle	2009-05-14	1	-0/+9
*	MIPS: Hook Cavium OCTEON cache init into cache.c	David Daney	2009-01-11	1	-0/+3
*	MIPS: New feature test macro cpu_has_mips_r	Ralf Baechle	2008-10-30	1	-0/+2
*	MIPS: Move headfiles to new location below arch/mips/include	Ralf Baechle	2008-10-11	1	-0/+219