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* MIPS: Add CPU support for Loongson1CYang Ling2016-10-041-0/+1
| | | | | | | | | | | | | | | | | Loongson1C is a 32-bit SoC designed by Loongson Technology Co., Ltd, with many features similar to Loongson1B. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: paul.burton@imgtec.com Cc: markos.chandras@imgtec.com Cc: james.hogan@imgtec.com Cc: kumba@gentoo.org Cc: macro@imgtec.com Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13303/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add probing & defs for VZ & guest featuresJames Hogan2016-05-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | Add a few new cpu-features.h definitions for VZ sub-features, namely the existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2 registers, and support for GuestID to dialias TLB entries belonging to different guests. Also add certain features present in the guest, with the naming scheme cpu_guest_has_*. These are added separately to the main options bitfield since they generally parallel similar features in the root context. A few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig registers, MAAR registers, and probably others in future) can be dynamically configured in the guest context, for which the cpu_guest_has_dyn_* macros are added. [ralf@linux-mips.org: Resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add perf counter featureJames Hogan2016-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add CPU feature for standard MIPS r2 performance counters, as determined by the Config1.PC bit. Both perf_events and oprofile probe this bit, so lets combine the probing and change both to use cpu_has_perf. This will also be used for VZ support in KVM to know whether performance counters exist which can be exposed to guests. [ralf@linux-mips.org: resolve conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13226/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add defs & probing of [X]ContextConfigJames Hogan2016-05-131-0/+1
| | | | | | | | | | | | | | | | | | The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or CP0_Config3.SM are set, and provide more control over which bits of CP0_[X]Context are set to the faulting virtual address on a TLB exception. KVM/VZ will need to be able to save and restore these registers in the guest context, so add the relevant definitions and probing of the ContextConfig feature in the root context first. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add defs & probing of BadInstr[P] registersJames Hogan2016-05-131-0/+2
| | | | | | | | | | | | | | | | | | | | The optional CP0_BadInstr and CP0_BadInstrP registers are written with the encoding of the instruction that caused a synchronous exception to occur, and the prior branch instruction if in a delay slot. These will be useful for instruction emulation in KVM, and especially for VZ support where reading guest virtual memory is a bit more awkward. Add CPU option numbers and cpu_has_* definitions to indicate the presence of each registers, and add code to probe for them using bits in the CP0_Config3 register. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add defs & probing of extended CP0_EBaseJames Hogan2016-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CP0_EBase register may optionally have a write gate (WG) bit to allow the upper bits to be written, i.e. bits 31:30 on MIPS32 since r3 (to allow for an exception base outside of KSeg0/KSeg1 when segmentation control is in use) and bits 63:30 on MIPS64 (which also implies the extension of CP0_EBase to 64 bits long). The presence of this feature will need to be known about for VZ support in order to correctly save and restore all the bits of the guest CP0_EBase register, so add CPU feature definition and probing for this feature. Probing the WG bit on MIPS64 can be a bit fiddly, since 64-bit COP0 register access instructions were UNDEFINED for 32-bit registers prior to MIPS r6, and it'd be nice to be able to probe without clobbering the existing state, so there are 3 potential paths: - If we do a 32-bit read of CP0_EBase and the WG bit is already set, the register must be 64-bit. - On MIPS r6 we can do a 64-bit read-modify-write to set CP0_EBase.WG, since the upper bits will read 0 and be ignored on write if the register is 32-bit. - On pre-r6 cores, we do a 32-bit read-modify-write of CP0_EBase. This avoids the potentially UNDEFINED behaviour, but will clobber the upper 32-bits of CP0_EBase if it isn't a simple sign extension (which also requires us to ensure BEV=1 or modifying the exception base would be UNDEFINED too). It is hopefully unlikely a bootloader would set up CP0_EBase to a 64-bit segment and leave WG=0. [ralf@linux-mips.org: Resolved merge conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Tested-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13223/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Separate XPA CPU feature into LPA and MVHJames Hogan2016-05-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | XPA (eXtended Physical Addressing) should be detected as a combination of two architectural features: - Large Physical Address (as per Config3.LPA). With XPA this will be set on MIPS32r5 cores, but it may also be set for MIPS64r2 cores too. - MTHC0/MFHC0 instructions (as per Config5.MVH). With XPA this will be set, but it may also be set in VZ guest context even when Config3.LPA in the guest context has been cleared by the hypervisor. As such, XPA is only usable if both bits are set. Update CPU features to separate these two features, with cpu_has_xpa requiring both to be set. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13112/ Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen2016-05-131-0/+1
| | | | | | | | | | | | | | | | | Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen2016-05-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12751/ Patchwork: https://patchwork.linux-mips.org/patch/13136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Detect DSP v3 supportZubair Lutfullah Kakakhel2016-05-131-0/+1
| | | | | | | | | | | | | | | | DSPv3 is supported on all MIPSr6 systems which indicate support for DSPv2. This doesn't require any changes to the kernel's handling of DSP resources. The patch is to detect support and indicate it in /proc/cpuinfo DSP v3 introduces a new instruction BPOSGE32C Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12918/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu: Convert MIPS_CPU_* defs to (1ull << x)James Hogan2016-05-131-41/+48
| | | | | | | | | | | | | | | | | The MIPS_CPU_* definitions have now filled the first 32-bits, and are getting longer since they're written in hex without zero padding. Adding my 8 extra MIPS_CPU_* definitions which I haven't upstreamed yet this is getting increasingly ugly as the comments get shifted progressively to the right. Its also error prone, and I've seen this cause mistakes on 3 separate occasions now, not helped by it being a conflict hotspot. Convert all the MIPS_CPU_* definitions to the form (1ull << x). Humans are better at incrementing than shifting. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10045/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu: Alter MIPS_CPU_* definitions to fill gapJames Hogan2016-05-131-8/+8
| | | | | | | | | | | | | | The MIPS_CPU_* definitions accidentally missed bits 27..30 when MIPS_CPU_EVA was added, and further definitions have continued from there. Shift all the definitions since MIPS_CPU_EVA right by 4 so there are no gaps. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10044/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add M6250 PRID & cpu_type_enum valuesPaul Burton2016-05-131-1/+2
| | | | | | | | | | | | | | | | Define the processor ID for the M6250 CPU and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12373/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add P6600 PRID & cpu_type_enum valuesPaul Burton2016-05-131-1/+2
| | | | | | | | | | | | | | | | Define the processor ID for the P6600 core and add a value to the enum cpu_type_enum for the core. [ralf@linux-mips.org: Fix merge conflict.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12342/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: <asm/cpu.h>: Reformat to 80 columns.Ralf Baechle2016-05-131-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton2016-05-131-0/+1
| | | | | | | | | | | | | | | | | | MIPSr6 introduces support for "Virtual Processors", which are conceptually similar to VPEs from the now-deprecated MT ASE. Detect whether the system supports VPs using the VP bit in Config5, adding cpu_has_vp for use by later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CPU identifiers and probing for Cavium CN73xx and CNF75xx processors.David Daney2016-05-131-0/+2
| | | | | | | | | | Add new processor identifiers for Cavium CN73xx and CNF75xx processors, and probe for them in cpu-probe.c Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define the legacy-NaN and 2008-NaN featuresMaciej W. Rozycki2016-01-201-0/+2
| | | | | | | | | | | | | | | Allocate CPU option bits and define macros for the legacy-NaN and 2008-NaN IEEE Std 754 MIPS architecture features. Unconditionally mark the legacy-NaN feature as present across hardware and emulated floating-point configurations. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11475/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu-features: Add cpu_has_ftlbJames Hogan2015-09-221-0/+1
| | | | | | | | | | | | | | | | Add cpu_has_ftlb, which specifies that an FTLB is present in addition to the VTLB, probed based on whether Config.MT == 4 (rather than 1 for standard JTLB). This is necessary since MIPS release 6 removes Config4.MMUExtDef, so the presence of the FTLB fields in Config4 must be determined from Config.MT instead. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for small (1KiB) page supportJames Hogan2015-09-031-0/+1
| | | | | | | | | | | Probe Config3 for small page support. This will be useful to give clues as to whether the PageGrain register exists. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10722/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add MIPS I6400 PRid and cputype identifiersMarkos Chandras2015-08-261-0/+2
| | | | | | | | | Add a Processor ID and CPU type for the MIPS I6400 core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: R12000: Enable branch prediction global historyJoshua Kinard2015-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The R12000 added a new feature to enhance branch prediction called "global history". Per the Vr10000 Series User Manual (U10278EJ4V0UM), Coprocessor 0, Diagnostic Register (22): """ If bit 26 is set, branch prediction uses all eight bits of the global history register. If bit 26 is not set, then bits 25:23 specify a count of the number of bits of global history to be used. Thus if bits 26:23 are all zero, global history is disabled. The global history contains a record of the taken/not-taken status of recently executed branches, and when used is XOR'ed with the PC of a branch being predicted to produce a hashed value for indexing the BPT. Some programs with small "working set of conditional branches" benefit significantly from the use of such hashing, some see slight performance degradation. """ This patch enables global history on R12000 CPUs and up by setting bit 26 in the branch prediction diagnostic register (CP0 $22) to '1'. Bits 25:23 are left alone so that all eight bits of the global history register are available for branch prediction. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ingenic: Add newer vendor IDsPaul Burton2015-06-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | Ingenic have actually varied the vendor/company ID of the XBurst cores across their range of SoCs, whilst keeping the product ID & revision constant... Add definitions for vendor IDs known to be used in some of Ingenic's newer SoCs, and handle them in the same way as the existing Ingenic vendor ID from the JZ4740. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Co-authored-by: Paul Cercueil <paul@crapouillou.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '4.0-fixes' into mips-for-linux-nextRalf Baechle2015-04-131-1/+2
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| * MIPS: Add support for XPA.Steven J. Hill2015-03-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add R16000 detectionJoshua Kinard2015-04-011-3/+3
| | | | | | | | | | | | | | | | | | | | | | This allows the kernel to correctly detect an R16000 MIPS CPU on systems that have those. Otherwise, such systems will detect the CPU as an R14000, due to similarities in the CPU PRId value. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add arch CDMM definitions and probingJames Hogan2015-03-311-0/+1
|/ | | | | | | | | | | | | | | | | | | Add architectural definitions and probing for the MIPS Common Device Memory Map (CDMM) region. When supported and enabled at a particular physical address, this region allows some number of per-CPU devices to be discovered and controlled via MMIO. A bit exists in Config3 to determine whether the feature is present, and a CDMMBase CP0 register allows the region to be enabled at a particular physical address. [ralf@linux-mips.org: Sort conflict with other patches.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-171-0/+1
| | | | | | | | | | | | | | | | | | | The LLBIT (bit 4) in the Config5 CP0 register indicates the software availability of the Load-Linked bit. This bit is only set by hardware and it has the following meaning: 0: LLB functionality is not supported 1: LLB functionality is supported. The following feature are also supported: - ERETNC instruction. Similar to ERET but it does not clear the LLB bit in the LLAddr register. - CP0 LLAddr/LLB bit must be set - LLbit is software accessible through the LLAddr[0] This will be used later on to emulate R2 LL/SC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2015-02-171-2/+5
| | | | | | | Add MIPS R6 to the ISA definitions Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add generic QEMU PRid and cpu type identifiersLeonid Yegoshin2015-02-161-0/+3
| | | | | | | | | Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)Kevin Cernekee2014-11-241-0/+1
| | | | | | | | | | | | | | | | This is a dual core (quad thread) BMIPS5000. It needs a little extra code to boot the second core (CPU2/CPU3), but for now we can treat it the same as a single core BMIPS5000. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8166/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: detect presence of the FRE & UFR bitsPaul Burton2014-11-241-0/+1
| | | | | | | | | | | | | | Detect the presence of the Config5 FRE & UFE bits, as indicated by the FREP bit in FPIR. Record this as a CPU option bit, and provide a cpu_has_fre macro to ease checking of that option bit. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: detect presence of MAARsPaul Burton2014-08-021-0/+1
| | | | | | | | | | | Detect the presence of MAAR using the MRP bit in Config5, and record that presence using a CPU option bit. A cpu_has_maar macro will then allow code to conditionalise upon the presence of MAARs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add new option for unique RI/XI exceptionsLeonid Yegoshin2014-08-021-0/+1
| | | | | | | | | | | MIPSr5 added support for unique exception codes for the Read-Inhibit and Execute-Inhibit exceptions. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu: Add new cpu option for Hardware Table Walker.Markos Chandras2014-08-021-0/+1
| | | | | | | | | | Moreover, report hardware page table walker support as 'htw' in the ASE list of /proc/cpuinfo, if the core implements this feature. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu-info: Change the cpu options variable to unsigned long longMarkos Chandras2014-08-021-28/+28
| | | | | | | | | | | | | | | Long integers which are 4 bytes in MIPS32 can't hold new CPU options anymore, so the type of the 'options' variable is changed to unsigned long long which allows 32 more cpu options to be defined for MIPS32 Also, re-arrange the 'options' struct member to avoid potential 4-byte alignment gap in the middle of the struct. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7324/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Loongson-3B supportHuacai Chen2014-07-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Add support for XLP5XXYonghong Song2014-05-301-0/+1
| | | | | | | | | | | Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by: Yonghong Song <ysong@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6871/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RM9000: Remove the now unused CPU_RM9000 definition.Ralf Baechle2014-05-231-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Add basic Loongson-3 definitionHuacai Chen2014-03-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6629/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Rename PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2Huacai Chen2014-03-311-2/+2
| | | | | | | | | | | | | | | | | | | Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by: Huacai Chen <chenhc@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6552/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-261-1/+1
| | | | | | | | | | | | | | The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add processor identifier for the M5150 processorLeonid Yegoshin2014-03-261-0/+1
| | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6595/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras2014-03-261-0/+1
| | | | | | | The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to indicate whether the core supports EVA or not. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add MIPS P5600 PRid and cputype identifiersJames Hogan2014-03-261-1/+2
| | | | | | | | | | Add a Processor ID and CPU type for the MIPS P5600 core. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6407/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+1
| | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-061-1/+1
| | | | | | | | | | | | The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Netlogic: Identify XLP 9XX chipJayachandran C2014-01-241-0/+1
| | | | | | | | | Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6274/
* MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-221-1/+1
| | | | | | | | | | | | | | | The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
* MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin2014-01-221-0/+2
| | | | | | | | | Add processor identifiers for UP and MT interAptiv processors. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6151/
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