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* MIPS: Select CONFIG_ARCH_USE_CMPXCHG_LOCKREF for MIPS64Paul Burton2015-09-031-0/+5
* MIPS: Get rid of finish_arch_switch().Ralf Baechle2015-09-031-25/+23
* MIPS: Use Ingenic-specific write combine attribute on all Ingenic platformsAlex Smith2015-09-031-1/+1
* MIPS: Fix definition of pgprot_writecombine()Alex Smith2015-09-031-0/+2
* MIPS: AT_HWCAP aux vector infrastructurePaul Burton2015-09-032-1/+11
* MIPS: Add definitions for extended contextPaul Burton2015-09-033-1/+68
* MIPS: Indicate FP mode in sigcontext sc_used_mathPaul Burton2015-09-031-0/+9
* MIPS: Use common FP sigcontext code for O32 compatPaul Burton2015-09-031-0/+3
* MIPS: Add offsets to sigcontext FP fields to struct mips_abiPaul Burton2015-09-031-0/+4
* MIPS: cevt-r4k: Migrate to new 'set-state' interfaceViresh Kumar2015-09-031-1/+0
* MIPS: Rearrange ENTRYLO field definitionsJames Hogan2015-09-031-25/+27
* MIPS: Probe for small (1KiB) page supportJames Hogan2015-09-032-0/+5
* MIPS: Refactor dumping of TLB registers for r3k/r4kJames Hogan2015-09-031-0/+1
* MIPS: Treat CP1 control registers as unsigned ints.Ralf Baechle2015-09-031-1/+1
* MIPS: Use unsigned int when reading CP0 registersChris Packham2015-09-031-2/+2
* MIPS: Introduce accessors for MSA vector registersPaul Burton2015-09-032-0/+194
* MIPS: Declare MSA MI10 instruction formatsLeonid Yegoshin2015-09-031-1/+30
* MIPS: Remove "__weak" definition from arch-specific linkage.hBjorn Helgaas2015-09-031-1/+0
* MIPS: Remove "weak" from mips_cdmm_phys_base() declarationBjorn Helgaas2015-09-031-2/+2
* MIPS: Remove "weak" from get_c0_fdc_int() declarationBjorn Helgaas2015-09-031-1/+1
* MIPS: Remove "weak" from get_c0_compare_int() declarationBjorn Helgaas2015-09-031-1/+1
* MIPS: MT: Remove "weak" from vpe_run() declarationBjorn Helgaas2015-08-261-1/+1
* MIPS: Remove "weak" from platform_maar_init() declarationBjorn Helgaas2015-08-261-1/+1
* MIPS: CPC: Remove "weak" from mips_cpc_phys_base() and make it staticBjorn Helgaas2015-08-261-10/+0
* MIPS: Drop CONFIG_RUNTIME_DEBUG & debug.hPaul Burton2015-08-261-48/+0
* MIPS: Set up FTLB probability for I6400Markos Chandras2015-08-261-0/+2
* MIPS: CM: Add support for reporting CM cache errorsMarkos Chandras2015-08-261-0/+9
* MIPS: mips-cm: Extend CM accessors for 64-bit CPUsMarkos Chandras2015-08-261-4/+44
* MIPS: CM: Add GCR_L2_CONFIG register accessorsPaul Burton2015-08-261-0/+11
* MIPS: mips-cm: Implement mips_cm_revisionPaul Burton2015-08-261-0/+21
* MIPS: Add cases for CPU_I6400Markos Chandras2015-08-261-0/+4
* MIPS: Add MIPS I6400 PRid and cputype identifiersMarkos Chandras2015-08-261-0/+2
* MIPS: Make set_pte() SMP safe.David Daney2015-08-051-0/+31
* MIPS: Flush RPS on kernel entry with EVAJames Hogan2015-08-031-0/+25
* Revert "MIPS: BCM63xx: Provide a plat_post_dma_flush hook"Florian Fainelli2015-08-031-10/+0
* MIPS: SMP: Don't increment irq_count multiple times for call function IPIsAlex Smith2015-08-031-2/+0
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-07-193-5/+4
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| * MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPUMarkos Chandras2015-07-191-1/+1
| * MIPS: SB1: Remove support for Pass 1 parts.Ralf Baechle2015-07-141-2/+1
| * MIPS: asm-offset.c: Patch up various comments refering to the old filename.Ralf Baechle2015-07-141-2/+2
* | mm: clean up per architecture MM hook header filesLaurent Dufour2015-07-182-15/+1
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* MIPS: c-r4k: Fix cache flushing for MT coresMarkos Chandras2015-07-101-0/+1
* MIPS, CPUFREQ: Fix spelling of Institute.Ralf Baechle2015-07-071-1/+1
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-2762-151/+441
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| * MIPS: spinlock: Adjust arch_spin_lock back-off timeMarkos Chandras2015-06-241-1/+1
| * MIPS: asmmacro: Ensure 64-bit FP registers are used with MSAMarkos Chandras2015-06-241-0/+11
| * MIPS: Replace smp_mb with release barrier function in unlocks.Leonid Yegoshin2015-06-212-2/+2
| * MIPS: i8259: DT supportPaul Burton2015-06-211-0/+1
| * MIPS: include errno.h for ENODEV in mips-cm.hPaul Burton2015-06-211-0/+1
| * MIPS: Define GCR_GIC_STATUS register fieldsPaul Burton2015-06-211-0/+4
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