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path: root/arch/mips/kernel/traps.c (follow)
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* MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney2009-06-171-4/+0
* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-171-1/+1
* MIPS: Use BUG_ON() where possible.Ralf Baechle2009-03-301-2/+1
* MIPS: R2: Fix problem with code that incorrectly modifies ebase.Chris Dearman2009-03-231-5/+7
* MIPS: Read watch registers with interrupts disabled.David Daney2009-01-301-1/+7
* MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle2009-01-301-2/+6
* MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney2009-01-111-0/+21
* MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle2008-10-301-0/+16
* MIPS: Consider value of c0_ebase when computing value of exception base.David Daney2008-10-301-4/+9
* MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.David Daney2008-10-111-5/+19
* [MIPS] SMTC: Fix holes in SMTC and FPU affinity support.Kevin D. Kissell2008-10-031-2/+4
* [MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto2008-09-211-6/+16
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-051-5/+7
* [MIPS] Fix data bus error recoveryThomas Bogendoerfer2008-09-051-2/+4
* [MIPS] kgdb: add arch support for the kernel's kgdb coreJason Wessel2008-07-301-0/+21
* [MIPS] Replace use of print_symbol with new %sP pointer format.Ralf Baechle2008-07-151-4/+4
* [MIPS] Remove board_watchpoint_handlerDavid Daney2008-07-151-6/+0
* [MIPS] Fix check for valid stack pointer during backtraceThomas Bogendoerfer2008-06-051-7/+9
* [MIPS] Fix handling of trap and breakpoint instructionsRalf Baechle2008-04-281-52/+37
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-12/+99
* [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman2008-04-281-1/+12
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-3/+4
* [MIPS] Added missing cases for rdhwr emulationChris Dearman2008-03-121-6/+25
* [MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman2007-12-141-3/+3
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-161-65/+3
* Use helpers to obtain task pid in printks (arch code)Alexey Dobriyan2007-10-191-1/+1
* [MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle2007-10-181-0/+11
* [MIPS] SYNC emulation for MIPS I processorsMaciej W. Rozycki2007-10-171-78/+86
* [MIPS] IP22: Fix warning.Ralf Baechle2007-10-161-6/+15
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-121-1/+2
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-121-13/+13
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-121-3/+3
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-121-0/+6
* [MIPS] Kill useless volatile keywordRalf Baechle2007-10-121-2/+2
* [MIPS] Maintain si_code field properly for FP exceptionsThiemo Seufer2007-08-271-3/+18
* [MIPS] SMTC: Fix duplicate status dumps on NMIThiemo Seufer2007-08-271-9/+1
* [MIPS] Fixup secure computing stuff.Ralf Baechle2007-07-311-1/+1
* Report that kernel is tainted if there was an OOPSPavel Emelianov2007-07-171-0/+1
* [MIPS] Make show_code static and add __user tagAtsushi Nemoto2007-07-131-3/+3
* [MIPS] Add some __user tagsAtsushi Nemoto2007-07-131-1/+1
* [MIPS] Sparse: Use NULL for pointerAtsushi Nemoto2007-07-121-1/+1
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-101-0/+6
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-1/+8
* [MIPS] FP affinity: Coding style cleanups Ralf Baechle2007-07-101-30/+29
* [MIPS] Remove unused watchpoint support and arch/mips/lib-{32,64}Atsushi Nemoto2007-07-101-1/+0
* [MIPS] Transform old-style macros to newer "__noreturn"Robert P. J. Day2007-07-101-1/+1
* [MIPS] Fix timer/performance interrupt detectionChris Dearman2007-07-061-4/+4
* [MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle2007-06-201-3/+17
* [MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.Ralf Baechle2007-06-111-0/+7
* [MIPS] SMTC: Don't continue in set_vi_srs_handler on detected bad arguments.Ralf Baechle2007-06-111-2/+3
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