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* MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: Allow ASID size to be determined at boot time."David Daney2013-05-162-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390. The original commit has several problems: 1) Doesn't work with 64-bit kernels. 2) Calls TLBMISS_HANDLER_SETUP() before the code is generated. 3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when only one call is needed. [ralf@linux-mips.org: Also revert the bits of the ASID patch which were hidden in the KVM merge.] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5242/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mti-next' of ↵Ralf Baechle2013-05-096-55/+84
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: microMIPS: Optimise 'strnlen' core library function.Steven J. Hill2013-05-091-1/+1
| | | | | | | | | | | | | | | | Optimise 'strnlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: microMIPS: Optimise 'strlen' core library function.Steven J. Hill2013-05-091-4/+5
| | | | | | | | | | | | | | | | Optimise 'strlen' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: microMIPS: Optimise 'strncpy' core library function.Steven J. Hill2013-05-091-15/+17
| | | | | | | | | | | | | | | | Optimise 'strncpy' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: microMIPS: Optimise 'memset' core library function.Steven J. Hill2013-05-091-30/+54
| | | | | | | | | | | | | | | | Optimise 'memset' to use microMIPS instructions and/or optimisations for binary size reduction. When the microMIPS ISA is not being used, the library function compiles to the original binary code. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: Allow ASID size to be determined at boot time.Steven J. Hill2013-05-082-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. [ralf@linux-mips.org: Added relevant part of fix https://patchwork.linux-mips.org/patch/5213/] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'mips-next-3.10' of ↵Ralf Baechle2013-05-081-7/+7
|\ \ | | | | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * | MIPS: Remove unneeded volatile from arch/mips/lib/bitops.cDavid Daney2013-05-081-7/+7
| |/ | | | | | | | | | | | | | | | | | | | | The operations on the bitmap pointers are protected by "memory" clobbering raw_local_irq_{save,restore}(), so there is no need for volatile here. By removing the volatile we get better code generation out of the compiler. Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4966/ Acked-by: John Crispin <blogic@openwrt.org>
* / MIPS: Get rid of the use of .macro in C code.Ralf Baechle2013-04-111-65/+84
|/ | | | | | It fails with LTO and probably has always been a fragile. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix logic errors in bitops.cDavid Daney2013-03-121-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 92d11594f6 (MIPS: Remove irqflags.h dependency from bitops.h) factored some of the bitops code out into a separate file (arch/mips/lib/bitops.c). Unfortunately the logic converting a bit mask into a boolean result was lost in some of the functions. We had: int res; unsigned long shifted_result_bit; . . . res = shifted_result_bit; return res; Which truncates off the high 32 bits (thus yielding an incorrect value) on 64-bit systems. The manifestation of this is that a non-SMP 64-bit kernel will not boot as the bitmap operations in bootmem.c are all screwed up. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Jim Quinlan <jim2101024@gmail.com> Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use CONFIG_CPU_MIPSR2 in csum_partial.SGabor Juhos2013-03-121-2/+2
| | | | | | | | | | | | | The csum_partial implementation contain optimalizations for the MIPS R2 instruction set. This optimization is never enabled however because the if directive uses the CPU_MIPSR2 constant which is not defined anywhere. Use the CONFIG_CPU_MIPSR2 constant instead. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-0110-50/+50
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: delay.c: Check BITS_PER_LONG instead of __SIZEOF_LONG__Geert Uytterhoeven2013-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | When building a 32-bit kernel for RBTX4927 with gcc version 4.1.2 20061115 (prerelease) (Ubuntu 4.1.1-21), I get: arch/mips/lib/delay.c:24:5: warning: "__SIZEOF_LONG__" is not defined As a consequence, __delay() always uses the 64-bit "dsubu" instruction. Replace the check for "__SIZEOF_LONG__ == 4" by "BITS_PER_LONG == 32" to fix this. Introduced by commit 5210edcd527773c227465ad18e416a894966324f [MIPS: Make __{,n,u}delay declarations match definitions and generic delay.h"] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Patchwork: https://patchwork.linux-mips.org/patch/4678/ Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix crash that occurs when function tracing is enabledAl Cooper2012-11-231-4/+4
| | | | | | | | | | | | | | A recent patch changed some irq routines from inlines to functions. These routines are called by the tracer code. Now that they're functions, if they are compiled for function tracing they will call the tracer and crash the system due to infinite recursion. The fix disables tracing in these functions by using "notrace" in the function definition. Signed-off-by: Al Cooper <alcooperx@gmail.com> Reviewed-by: David Daney <david.daney@cavium.com> Pathchwork: https://patchwork.linux-mips.org/patch/4564/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpusJim Quinlan2012-11-092-1/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | For non MIPSr2 processors, such as the BMIPS 5000, calls to arch_local_irq_disable() and others may be preempted, and in doing so a stale value may be restored to c0_status. This fix disables preemption for such processors prior to the call and enables it after the call. Those functions that needed this fix have been "outlined" to mips-atomic.c, as they are no longer good candidates for inlining. This bug was observed in a BMIPS 5000, occuring once every few hours in a continuous reboot test. It was traced to the write_lock_irq() function which was being invoked in release_task() in exit.c. By placing a number of "nops" inbetween the mfc0/mtc0 pair in arch_local_irq_disable(), which is called by write_lock_irq(), we were able to greatly increase the occurance of this bug. Similarly, the application of this commit silenced the bug. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove irqflags.h dependency from bitops.hJim Quinlan2012-11-092-1/+180
| | | | | | | | | | | | | | | The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Restore pagemask after dumping the TLB.Ralf Baechle2012-10-171-1/+3
| | | | | | Or bad things might happen if the last TLB entry isn't a basic size page. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make __{,n,u}delay declarations match definitions and generic delay.hDavid Daney2012-10-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | | At some recent point arch/mips/include/asm/delay.h has started being included into csrc-octeon.c where the __?delay() functions are defined. This causes a compile failure due to conflicting declarations and definitions of the functions. It turns out that the generic definitions in arch/mips/lib/delay.c also conflict. Proposed fix: Declare the functions to take unsigned long parameters just like asm-generic (and x86) does. Update __delay to agree (__ndelay and __udelay need no change). Bonus: Get rid of 'inline' from __delay() definition, as it is globally visible, and the compiler should be making this decision itself (it does in fact inline the function without being told to). Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: introduce CPU_GENERIC_DUMP_TLBFlorian Fainelli2012-08-221-20/+1
| | | | | | | | Allows us not to duplicate more lines in arch/mips/lib/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3329/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: Unify memcpy.S and memcpy-inatomic.SDavid Daney2012-07-233-452/+12
| | | | | | | | | | | | We can save the 451 lines of code that comprise memcpy-inatomic.S at the expense of a single instruction in the memcpy prolog. We also use an additional register (t6), so this may cause increased register pressure in some places as well. But I think the reduced maintenance burden, of not having two nearly identical implementations, makes it worth it. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: use the the PCI controller's io_map_baseMichael S. Tsirkin2012-01-311-2/+2
| | | | | | | | | | | | | | | commit eab90291d35438bcebf7c3dc85be66d0f24e3002 (mips: switch to GENERIC_PCI_IOMAP) failed to take into account the PCI controller's io_map_base for mapping IO BARs. This also caused a new warning on mips. Fix this, without re-introducing code duplication, by setting NO_GENERIC_PCI_IOPORT_MAP and supplying a mips-specific __pci_ioport_map. Reported-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-01-141-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits) MIPS: Delete unused function add_temporary_entry. MIPS: Set default pci cache line size. MIPS: Flush huge TLB MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM. MIPS: Octeon: Add support for OCTEON II PCIe MIPS: Octeon: Update PCI Latency timer and enable more error reporting. MIPS: Alchemy: Update cpu-feature-overrides MIPS: Alchemy: db1200: Improve PB1200 detection. MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code. MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller MIPS: Alchemy: irq: register pm at irq init time MIPS: Alchemy: Touchscreen support on DB1100 MIPS: Alchemy: Hook up IrDA on DB1000/DB1100 net/irda: convert au1k_ir to platform driver. MIPS: Alchemy: remove unused board headers MTD: nand: make au1550nd.c a platform_driver MIPS: Netlogic: Mark Netlogic chips as SMT capable MIPS: Netlogic: Add support for XLP 3XX cores MIPS: Netlogic: Merge some of XLR/XLP wakup code MIPS: Netlogic: Add default XLP config. ... Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c, traps.c} and drivers/tty/serial/Makefile
| * MIPS: Netlogic: Add XLP makefiles and configJayachandran C2011-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | - Add CPU_XLP and NLM_XLR_BOARD to arch/mips/Kconfig for Netlogic XLP boards - Update mips Makefiles to add XLP Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mips: switch to GENERIC_PCI_IOMAPMichael S. Tsirkin2011-11-281-26/+0
|/ | | | | | | | mips copied pci_iomap from generic code, probably to avoid pulling the rest of iomap.c in. Since that's in a separate file now, we can reuse the common implementation. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* MIPS: Kconfig and Makefile update for Netlogic XLR/XLSJayachandran C2011-05-191-0/+1
| | | | | | | | | | Add NLM_XLR_BOARD, CPU_XLR and other config options Makefile updates, mostly based on r4k Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Fix common misspellingsLucas De Marchi2011-03-311-1/+1
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* MIPS: Separate two consecutive loads in memset.STony Wu2010-12-161-2/+2
| | | | | | | | | | | | | | | | | | partial_fixup is used in noreorder block. Separating two consecutive loads can save one cycle on processors with GPR intrelock and can fix load-use on processors that need a load delay slot. Also do so for fwd_fixup. [Ralf: Only R2000/R3000 class processors are lacking the the load-user interlock and even some of those got it retrofitted. With R2000/R3000 being fairly uncommon these days the impact of this bug should be minor.] Signed-off-by: Tony Wu <tung7970@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1768/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: libgcc.h: Checkpatch cleanupAndrea Gelmini2010-04-121-2/+1
| | | | | | | | | | | | arch/mips/lib/libgcc.h:21: ERROR: open brace '{' following union go on the same line Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> To: linux-kernel@vger.kernel.org Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-mips@linux-mips.org Cc: linux-sh@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/1007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: delay: Fix use of current_cpu_data in preemptable code.Ralf Baechle2010-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | This may lead to warnings like: BUG: using smp_processor_id() in preemptible [00000000] code: reboot/1989 caller is __udelay+0x14/0x70 Call Trace: [<ffffffff8110ad28>] dump_stack+0x8/0x34 [<ffffffff812dde04>] debug_smp_processor_id+0xf4/0x110 [<ffffffff812d90bc>] __udelay+0x14/0x70 [<ffffffff81378274>] md_notify_reboot+0x12c/0x148 [<ffffffff81161054>] notifier_call_chain+0x64/0xc8 [<ffffffff811614dc>] __blocking_notifier_call_chain+0x64/0xc0 [<ffffffff8115566c>] kernel_restart_prepare+0x1c/0x38 [<ffffffff811556cc>] kernel_restart+0x14/0x50 [<ffffffff8115581c>] SyS_reboot+0x10c/0x1f0 [<ffffffff81103684>] handle_sysn32+0x44/0x84 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix __ndelay build error and add 'ull' suffix for 32-bit kernelAtsushi Nemoto2009-06-171-2/+2
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Outline udelay and fix a few issues.Ralf Baechle2009-06-082-2/+58
| | | | | | | | | | | | | | | Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle2009-05-141-0/+9
| | | | | | | | Beyond the requirements of the architecture standard Cavium also supports 8k and 32k pages. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: IP27: Switch from DMA_IP27 to DMA_COHERENTRalf Baechle2009-01-302-2/+2
| | | | | | | | The special IP27 DMA code selected by DMA_IP27 has been removed a while ago turning DMA_IP27 into almost a nop. Also fixup the broken logic of its last users memcpy.S and memcpy-inatomic.s. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook up Cavium OCTEON in arch/mips.David Daney2009-01-111-0/+1
| | | | | | | | | | Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi2008-10-272-0/+2
| | | | | | | | | | | | We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.Ralf Baechle2008-10-111-11/+24
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP checksums: Remove unncessary .set pseudosRalf Baechle2008-10-111-12/+0
| | | | | | They possibly silence meaningful warnings ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.Ralf Baechle2008-10-111-10/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix 64-bit IP checksum codeAtsushi Nemoto2008-09-211-4/+17
| | | | | | | | | | | | Use unsigned loads to avoid possible misscalculation of IP checksums. This bug was instruced in f761106cd728bcf65b7fe161b10221ee00cf7132 (lmo) / ed99e2bc1dc5dc54eb5a019f4975562dbef20103 (kernel.org). [Original fix by Atsushi. Improved instruction scheduling and fix for unaligned unsigned load by me -- Ralf] Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* iomap: fix 64 bits resources on 32 bitsBenjamin Herrenschmidt2008-04-291-2/+2
| | | | | | | | | | | | | | Almost all implementations of pci_iomap() in the kernel, including the generic lib/iomap.c one, copies the content of a struct resource into unsigned long's which will break on 32 bits platforms with 64 bits resources. This fixes all definitions of pci_iomap() to use resource_size_t. I also "fixed" the 64bits arch for consistency. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Export __ucmpdi2 to modules.Ralf Baechle2008-03-121-0/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Eleminate local symbols from the symbol table.Ralf Baechle2008-01-297-281/+282
| | | | | | | | | These symbols appear in oprofile output, stacktraces and similar but only make the output harder to read. Many identical symbol names such as "both_aligned" were also being used in multiple source files making it impossible to see which file actually was meant. So let's get rid of them. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP28: added cache barrier to assembly routinesThomas Bogendoerfer2008-01-293-0/+16
| | | | | | | | | | | IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Put cast inside macro instead of all the callersAndrew Sharp2008-01-291-6/+6
| | | | | | | | | | Since all the callers of the PHYS_TO_XKPHYS macro call with a constant, put the cast to LL inside the macro where it really should be rather than in all the callers. This makes macros like PHYS_TO_XKSEG_UNCACHED work without gcc whining. Signed-off-by: Andrew Sharp <andy.sharp@onstor.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] R4000/R4400 daddiu erratum workaroundMaciej W. Rozycki2008-01-295-31/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This complements the generic R4000/R4400 errata workaround code and adds bits for the daddiu problem. In most places it just modifies handwritten assembly code so that the assembler is allowed to use a temporary register as daddiu may now be treated as a macro that expands to a sequence of li and daddu. It is the AT register or, where AT is unavailable or used explicitly for another purpose, an explicitly-named register is selected, using the .set at=<reg> feature added recently to gas. This feature is only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the workaround remains disabled, the required version of binutils stays unchanged. Similarly, daddiu instructions put in branch delay slots in noreorder fragments are now taken out of them and the assembler is allowed to reorder them itself as possible (which it does making the whole idea of scheduling them into delay slots manually questionable). Also in the very few places where such a simple conversion was not possible, a handcoded longer sequence is implemented. Other than that there are changes to code responsible for building the TLB fault and page clear/copy handlers to avoid daddiu as appropriate. These are only effective if the erratum is verified to be present at the run time. Finally there is a trivial update to __delay(), because it uses daddiu in a branch delay slot. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-121-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add __cmpdi2Ralf Baechle2007-08-272-1/+28
| | | | | | | Certain 32-bit kernel configurations seem to be able to cause references, this was observed with gcc 4.1.2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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