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2021-12-22arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCXBjorn Andersson1-2/+2
The SM6125_VDDCX constant is introduced through a separate branch and is not available in the dts branch. Temporarily replace the constant with it's value to avoid the build breakage. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-12-21arm64: dts: qcom: sm8450-qrd: Enable USB nodesVinod Koul1-0/+23
Enable the usb phy and usb controller in peripheral mode. This helps to get the adb working with the QRD board. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211216110813.658384-2-vkoul@kernel.org
2021-12-21arm64: dts: qcom: sm8450: Add usb nodesVinod Koul1-0/+89
SM8450 features a single USB controller which connects to both HS and SS phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211216110813.658384-1-vkoul@kernel.org
2021-12-21ARM: dts: aspeed: add LCLK setting into LPC KCS nodesJae Hyun Yoo2-0/+8
If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC KCS node as one of required properties to enable the LCLK by the LPC KCS driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20211108190200.290957-5-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21dt-bindings: ipmi: bt-bmc: add 'clocks' as a required propertyJae Hyun Yoo1-0/+2
If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtsi change in this patch series should be applied along with, and dtbs should be re-compiled after applying this series since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211108190200.290957-3-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: add LCLK setting into LPC IBT nodeJae Hyun Yoo3-0/+3
If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC IBT node as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20211108190200.290957-2-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: p10: Add TPM deviceEddie James2-0/+10
Add the Nuvoton NPCT75X, a TIS I2C TPM. Modified Eddie's change to include the general compatible string, and combine the rainier and everest patches. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211208191758.20517-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: p10: Enable USB host portsEddie James2-1/+17
Ensure both controllers are enabled on, and add GPIO hog for USB power control to set the USB power to always on. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211208170641.13322-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: Add TYAN S8036 BMC machineAli El-Haj-Mahmoud2-0/+471
The TYAN S8036 is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Ali El-Haj-Mahmoud <aaelhaj@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211130180110.2217042-1-aaelhaj@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart configOskar Senft1-0/+16
Configure the vuart in such a way that it does not inhibit the SuperIO's UART from functioning correctly. This allows the same DTS to be used for both configurations with SuperIO and VUART (depending on the BIOS build). The decision on whether to actually enable VUART can then be made at runtime. This change also enables the new uart_routing driver for the SuperIO case. Signed-off-by: Oskar Senft <osk@google.com> Link: https://lore.kernel.org/r/20211130184855.1779353-1-osk@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: Adding Facebook Bletchley BMCHoward Chiu2-0/+757
Initial introduction of Facebook Bletchley equipped with Aspeed 2600 BMC SoC. Signed-off-by: Howard Chiu <howard.chiu@quantatw.com> Link: https://lore.kernel.org/r/20211207094923.422422-1-howard.chiu@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-12-21ARM: dts: aspeed: g220a: Enable secondary flashLei YU1-0/+12
Enable the secondary flash of the g220a's BMC and the wdt2. Signed-off-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20211210093623.2140640-1-yulei.sh@bytedance.com Signed-off-by: Joel Stanley <joel@jms.id.au>