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* MIPS: Support for hybrid FPRsPaul Burton2014-11-241-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove useless parenthesesRalf Baechle2014-11-242-2/+2
| | | | | | | | | | | | | | | Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix build with binutils 2.24.51+Manuel Lauss2014-11-071-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cp1emu: Fix ISA restrictions for cop1x_op instructionsMarkos Chandras2014-10-211-2/+2
| | | | | | | | | | | | | | | | | | | Commit 08a07904e1828 ("MIPS: math-emu: Remove most ifdefery") removed the #ifdef ISA conditions and switched to runtime detection. However, according to the instruction set manual, the cop1x_op instructions are available in >=MIPS32r2 as well. This fixes a problem on MIPS32r2 with the ntpd package which failed to execute with a SIGILL exit code due to the fact that a madd.d instruction was not being emulated. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: 08a07904e1828 ("MIPS: math-emu: Remove most ifdefery") Cc: <stable@vger.kernel.org> # v3.16+ Cc: linux-mips@linux-mips.org Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/8173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix MFC1 & MFHC1 emulation for 64-bit MIPS systemsPaul Burton2014-09-261-3/+3
| | | | | | | | | | | | | | | | | | | Commit bbd426f542cb "MIPS: Simplify FP context access" modified the SIFROMREG & SIFROMHREG macros such that they return unsigned rather than signed 32b integers. I had believed that to be fine, but inadvertently missed the MFC1 & MFHC1 cases which write to a struct pt_regs regs element. On MIPS32 this is fine, but on 64 bit those saved regs' fields are 64 bit wide. Using unsigned values caused the 32 bit value from the FP register to be zero rather than sign extended as the architecture specifies, causing incorrect emulation of the MFC1 & MFHc1 instructions. Fix by reintroducing the casts to signed integers, and therefore the sign extension. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: stable@vger.kernel.org # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7848/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix instruction decoding.Rob Kendrick2014-07-301-1/+1
| | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reduce code duplication.Ralf Baechle2014-06-261-13/+6
| | | | | | | The fix in the preceeding commit did do exactly the same thing in two places showing some code cleanup was due. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Work around limitations of older GCC.Ralf Baechle2014-06-161-3/+15
| | | | | | | | | | Older GCC doesn't get named initializations of anonymous structs right, that is members are not initializable in the containing structure through name however old style initializations are working fine. The issue exists with gcc up to 4.5.x. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Enable use of FPUDavid Daney2014-05-301-1/+5
| | | | | | | | | | | | | | | | | | | | Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add IEEE754 exception statistics to debugfsDeng-Cheng Zhu2014-05-302-9/+32
| | | | | | | | | | | | | | | | | | | | Sometimes it's useful to let the user, while doing performance research, know what in the IEEE754 exceptions has caused many times of FP emulation when running a specific application. This patch adds 5 more files to /sys/kernel/debug/mips/fpuemustats/, whose filenames begin with "ieee754". These stats are in addition to the existing cp1ops, cp1xops, errors, loads and stores, which may not be useful in understanding the reasons of ieee754 exceptions. [ralf@linux-mips.org: Fixed reject due to other changes to the kernel FP assist software.] Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Cc: james.hogan@imgtec.com Patchwork: http://patchwork.linux-mips.org/patch/7044/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reduce microMIPS bloat.Ralf Baechle2014-05-231-0/+7
| | | | | | | | Move microMIPS32_to_MIPS32() to a separate file which only gets built for mipsMIPS configurations; for other configurations the optimizer eleminates calls to microMIPS32_to_MIPS32(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Switch to using the MIPS rounding modes.Ralf Baechle2014-05-2315-91/+63
| | | | | | | | | | Previously math-emu was using the IEEE-754 constants internally. These were differing by having the constants for rounding to +/- infinity switched, so a conversion was necessary. This would be entirely avoidable if the MIPS constants were used throughout, so get rid of the bloat. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Nuke alternative names for IEEE-754 rounding modes.Ralf Baechle2014-05-233-6/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sort out mm_isBranchInstr.Ralf Baechle2014-05-231-201/+0
| | | | | | | | | | | | | | | | | | | | | | | | mm_isBranchInstr() did reside in the math emu code even though it logically is separate and also is used outside the math emu code. In addition GCC 4.9.0 leaves the following unnnecessarily bloated function body for a non-microMIPS configuration: <mm_isBranchInstr>: 105c: afa50004 sw a1,4(sp) 1060: afa60008 sw a2,8(sp) 1064: afa7000c sw a3,12(sp) 1068: 03e00008 jr ra 106c: 00001021 move v0,zero which stores arguments that are never going to be used on the stack frame. Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr() into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function which only invokes __mm_isBranchInstr() on microMIPS configurations. This shaves off 112 bytes off the kernel and improves code flow a bit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Inline fpu_emulator_init_fpu()Ralf Baechle2014-05-232-43/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Cleanup coding style.Ralf Baechle2014-05-2334-641/+497
| | | | | | | | | | | | o Only define variables in the outermost block o One empty line at most o Format comments as per CodingStyle o Update FSF address in licensing term comment o Spell FPU and MIPS in all capitals. o Remove ####-type of lines in comments. o Try to make things a bit most consistent between sp_*.c / dp_*.c files. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Cleanup definition of structs describe sp/dp floats.Ralf Baechle2014-05-235-80/+67
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Rename get_rounding() functions.Ralf Baechle2014-05-232-10/+10
| | | | | | | | There are two version of get_rounding(), one for single precision, one for double precision. Add a ieee754sp_ rsp. ieee754dp_ prefix for clarity. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Get rid of the useless parts of exception handling.Ralf Baechle2014-05-2332-263/+92
| | | | | | All it really did was throw a printk for no obvious reason. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Move various objects into an ar library.Ralf Baechle2014-05-231-6/+7
| | | | | | | | | | | | | | | ieee754d.o contains only debug code and dp_sqrt.o and sp_sqrt.o contain code which for MIPS I/II/III systems we don't want to link. Again the savings can be considerable for some systems: $ mips-linux-size --totals ieee754d.o dp_sqrt.o sp_sqrt.o text data bss dec hex filename 1624 0 0 1624 658 ieee754d.o 2016 0 0 2016 7e0 dp_sqrt.o 736 0 0 736 2e0 sp_sqrt.o 4376 0 0 4376 1118 (TOTALS) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Inline ieee754sp_issnan and ieee754dp_issnan.Ralf Baechle2014-05-234-4/+2
| | | | | | Shaves another 16 bytes off but more importantly avoids function calls. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove unused code.Ralf Baechle2014-05-2321-699/+6
| | | | | | Shrinks the FPU emulator by 4528 bytes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove unused ieee754sp_bestnan() and ieee754dp_bestnan().Ralf Baechle2014-05-234-26/+0
| | | | | | | Both are unused since lmo commit fdffbafbb38723618626c70ffdc6ff9175cdffa2 [Lots of FPU bug fixes from Kjeld Borch Egevang.] Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Inline ieee754dp_finite and ieee754dp_finite().Ralf Baechle2014-05-235-12/+10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Eleminate duplicate definitions of identical macros.Ralf Baechle2014-05-238-63/+33
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Use SPSIGN() rather than DPSIGN() in ieee754sp_sub().Ralf Baechle2014-05-231-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Replace DP_MBITS with DP_FBITS and SP_MBITS with SP_FBITS.Ralf Baechle2014-05-2325-100/+100
| | | | | | | Both were defined as 23 rsp. 52 though the mentissa is actually a bit more than the fraction. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Call ieee754di_xcpt, not ieee754si_xcpt in ieee754dp_cmp.Ralf Baechle2014-05-231-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Cleanup stdarg usage including apparently bogus comment.Ralf Baechle2014-05-234-8/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove #if 1 and dead code from its #else branch.Ralf Baechle2014-05-231-10/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Cleanup ieee754si_indef() / ieee754di_indef().Ralf Baechle2014-05-231-6/+10
| | | | | | | | LONG_LONG_MAX is a symbol defined in <limits.h> which may not be available so better rely on something provided by a kernel header. While at it, turn these function-like macros into inline functions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Convert debug printks to pr_debug getting.Ralf Baechle2014-05-232-16/+9
| | | | | | And another bunch of #ifdefs bite the dust. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Get rid of unuable extended precision support.Ralf Baechle2014-05-231-3/+0
| | | | | | No usable functionality and nothig does ever define IEEE854_XP anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove most ifdefery.Ralf Baechle2014-05-212-82/+133
| | | | | | | | Most of these tests should be runtime tests. This also finally means that on a MIPS III systems MIPS IV opcodes are going to result in an exception as they're supposed to. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Turn macros into functions where possible.Ralf Baechle2014-05-2139-131/+143
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Harden ieee754int.h against multiple inclusion.Ralf Baechle2014-05-211-1/+4
| | | | | | | The header file had no include guards; this only happened to work because the file only contains macro definitions and protypes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reformat code according to coding style.Ralf Baechle2014-05-217-133/+140
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Move all debug fs code to a separate file.Ralf Baechle2014-05-213-56/+62
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove fine example of cargo cult programming.Ralf Baechle2014-05-211-7/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Header file weeding.Ralf Baechle2014-05-217-29/+12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Use helpers to manipulate CAUSEF_BD flag.Ralf Baechle2014-05-212-8/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Get rid of typedefs.Ralf Baechle2014-05-2140-212/+212
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Use English spelling of `constant' rather than Danish.Ralf Baechle2014-05-212-8/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Mark exception handling functions as __cold.Ralf Baechle2014-05-217-16/+23
| | | | | | | Optimizes the code flow and shaves of half a percent of the math-emu code size. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Use __BITFIELD_FIELD to eleminate redundant definitions.Ralf Baechle2014-05-211-63/+23
| | | | | | | Union _ieee754sp was even duplicated even though there are no endian dependencies in it all. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2014-03-311-3/+3
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| * MIPS: math-emu: Fix prefx detection and COP1X function field definitionDeng-Cheng Zhu2014-03-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running applications which contain the instruction "prefx" on FPU-less CPUs, a message "Illegal instruction" will be seen. This instruction is supposed to be ignored by the FPU emulator. However, its current detection and function field encoding are incorrect. This patch fix the issue. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6608/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Clear upper bits of FP registers on emulator writesPaul Burton2014-03-261-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upper bits of an FP register are architecturally defined as unpredictable following an instructions which only writes the lower bits. The prior behaviour of the kernel is to leave them unmodified. This patch modifies that to clear the upper bits to zero. This is what the MSA architecture reference manual specifies should happen for its wider registers and is still permissible for scalar FP instructions given the bits unpredictability there. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: sergei.shtylyov@cogentembedded.com Patchwork: https://patchwork.linux-mips.org/patch/6435/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Move & rename fpu_emulator_{save,restore}_contextPaul Burton2014-03-261-75/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions aren't directly related to the FPU emulator at all, they simply copy between a thread's saved context & a sigcontext. Thus move them to the appropriate signal files & rename them accordingly. This makes it clearer that the functions don't require the FPU emulator in any way. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6422/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Simplify FP context accessPaul Burton2014-03-262-22/+36
|/ | | | | | | | | | | | | | | | This patch replaces the fpureg_t typedef with a "union fpureg" enabling easier access to 32 & 64 bit values. This allows the access macros used in cp1emu.c to be simplified somewhat. It will also make it easier to expand the width of the FP registers as will be done in a future patch in order to support the 128 bit registers introduced with MSA. No behavioural change is intended by this patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6532/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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