| Commit message (Expand) | Author | Age | Files | Lines |
* | [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants. | Ralf Baechle | 2006-11-30 | 1 | -3/+7 |
* | [MIPS] Remove redundant r4k_blast_icache() calls | Atsushi Nemoto | 2006-11-30 | 1 | -8/+4 |
* | [MIPS] Remove __flush_icache_page | Atsushi Nemoto | 2006-10-02 | 1 | -77/+0 |
* | [MIPS] c-r4k: Convert init functions from inline to __init. | Ralf Baechle | 2006-09-27 | 1 | -10/+10 |
* | [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache. | Atsushi Nemoto | 2006-09-27 | 1 | -2/+2 |
* | [MIPS] Retire flush_icache_page from mm use. | Ralf Baechle | 2006-09-27 | 1 | -1/+1 |
* | [MIPS] c-r4k: Typo fix. | Ralf Baechle | 2006-09-27 | 1 | -1/+1 |
* | [MIPS] vr41xx: Replace magic number for P4K bit with symbol. | Yoichi Yuasa | 2006-07-13 | 1 | -1/+1 |
* | [MIPS] vr41xx: Changed workaround to recommended method | Yoichi Yuasa | 2006-07-13 | 1 | -4/+3 |
* | [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80. | Yoichi Yuasa | 2006-07-13 | 1 | -1/+3 |
* | [MIPS] Use the proper technical term for naming some of the cache macros. | Ralf Baechle | 2006-07-13 | 1 | -4/+4 |
* | Remove obsolete #include <linux/config.h> | Jörn Engel | 2006-06-30 | 1 | -1/+0 |
* | [MIPS] 74K: Assume it will also have an AR bit in config7 | Ralf Baechle | 2006-06-29 | 1 | -0/+1 |
* | [MIPS] Treat CPUs with AR bit as physically indexed. | Ralf Baechle | 2006-06-29 | 1 | -3/+8 |
* | [MIPS] Fix handling of 0 length I & D caches. | Chris Dearman | 2006-06-29 | 1 | -23/+41 |
* | [MIPS] MIPS32/MIPS64 secondary cache management | Chris Dearman | 2006-06-29 | 1 | -5/+18 |
* | [MIPS] Save write-only Config.OD from being clobbered | Sergei Shtylyov | 2006-06-06 | 1 | -0/+34 |
* | [MIPS] Treat R14000 like R10000. | Kumba | 2006-06-01 | 1 | -0/+4 |
* | [MIPS] Fix deadlock on MP with cache aliases. | Ralf Baechle | 2006-06-01 | 1 | -9/+30 |
* | [MIPS] Add missing 34K processor IDs | Nigel Stephens | 2006-06-01 | 1 | -0/+1 |
* | [MIPS] Use __ffs() instead of ffs() for waybit calculation. | Atsushi Nemoto | 2006-04-19 | 1 | -8/+8 |
* | [MIPS] Handle IDE PIO cache aliases on SMP. | Ralf Baechle | 2006-04-19 | 1 | -0/+1 |
* | [MIPS] Fix tx49_blast_icache32_page_indexed. | Atsushi Nemoto | 2006-04-19 | 1 | -1/+2 |
* | [MIPS] TX49XX has prefetch. | Atsushi Nemoto | 2006-03-21 | 1 | -0/+1 |
* | [MIPS] local_r4k_flush_cache_page fix | Atsushi Nemoto | 2006-03-18 | 1 | -4/+9 |
* | [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. | Ralf Baechle | 2006-02-28 | 1 | -5/+11 |
* | [MIPS] Add protected_blast_icache_range, blast_icache_range, etc. | Atsushi Nemoto | 2006-02-14 | 1 | -90/+14 |
* | [MIPS] Remove wrong __user tags. | Atsushi Nemoto | 2006-02-07 | 1 | -4/+3 |
* | MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. | Ralf Baechle | 2006-01-10 | 1 | -2/+2 |
* | Rename page argument of flush_cache_page to something more descriptive. | Ralf Baechle | 2005-10-29 | 1 | -16/+17 |
* | Cleanup the mess in cpu_cache_init. | Ralf Baechle | 2005-10-29 | 1 | -1/+1 |
* | Add/Fix missing bit of R4600 hit cacheop workaround. | Thiemo Seufer | 2005-10-29 | 1 | -0/+1 |
* | Minor code cleanup. | Thiemo Seufer | 2005-10-29 | 1 | -15/+15 |
* | More .set push/pop. | Thiemo Seufer | 2005-10-29 | 1 | -2/+2 |
* | Let r4600 PRID detection match only legacy CPUs, cleanups. | Thiemo Seufer | 2005-10-29 | 1 | -2/+2 |
* | Avoid SMP cacheflushes. This is a minor optimization of startup but | Ralf Baechle | 2005-10-29 | 1 | -3/+2 |
* | More AP / SP bits for the 34K, the Malta bits and things. Still wants | Ralf Baechle | 2005-10-29 | 1 | -2/+1 |
* | Mark a few variables __read_mostly. | Ralf Baechle | 2005-10-29 | 1 | -1/+7 |
* | MIPS R2 instruction hazard handling. | Ralf Baechle | 2005-10-29 | 1 | -0/+1 |
* | Better interface to run uncached cache setup code. | Thiemo Seufer | 2005-10-29 | 1 | -4/+2 |
* | Sparseify MIPS. | Ralf Baechle | 2005-10-29 | 1 | -3/+4 |
* | Base Au1200 2.6 support. | Pete Popov | 2005-10-29 | 1 | -0/+4 |
* | Use intermediate variable. | Thiemo Seufer | 2005-10-29 | 1 | -3/+3 |
* | Moves a test which determines if we actually need to perform a | Ralf Baechle | 2005-10-29 | 1 | -7/+7 |
* | Update MIPS to use the 4-level pagetable code thereby getting rid of | Ralf Baechle | 2005-10-29 | 1 | -1/+3 |
* | 25Kf is also physically indexed. | Ralf Baechle | 2005-10-29 | 1 | -0/+1 |
* | 20Kc and SB1 don't suffer from aliases. | Ralf Baechle | 2005-10-29 | 1 | -0/+2 |
* | Move missplaced code line to the right place. | Ralf Baechle | 2005-10-29 | 1 | -3/+2 |
* | Use hardware mechanism to deal with cache aliases in the 24K. | Ralf Baechle | 2005-10-29 | 1 | -2/+10 |
* | Remove old wrong bits of cache code. | Ralf Baechle | 2005-10-29 | 1 | -3/+0 |