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path: root/arch/mips/mm/tlbex.c (follow)
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* MIPS: Remove dead case label.David Daney2009-06-171-1/+0
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-171-1/+2
* MIPS: Fold the TLB refill at the vmalloc path if possible.David Daney2009-06-171-24/+49
* MIPS: Replace some magic numbers with symbolic values in tlbex.cDavid Daney2009-06-171-8/+26
* MIPS: Alchemy: MIPS hazard workarounds are not required.Manuel Lauss2009-03-301-1/+1
* MIPS: Alchemy: unify CPU model constants.Manuel Lauss2009-03-301-7/+1
* MIPS: NEC VR5500 processor support fixupShinya Kuribayashi2009-03-111-0/+1
* MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney2009-01-111-0/+1
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-051-3/+3
* [MIPS] R4700: Fix build_tlb_probe_entryThomas Bogendoerfer2008-06-051-1/+2
* [MIPS] Add missing 4KEC TLB refill handlerThomas Bogendoerfer2008-04-011-0/+1
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-35/+35
* [MIPS] Split the micro-assembler from tlbex.c.Thiemo Seufer2008-02-011-959/+341
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-291-0/+2
* [MIPS] tlbex.c: cleanup debug codeFranck Bui-Huu2008-01-291-57/+26
* [MIPS] tlbex.c: use __cacheline_aligned instead of __tlb_handler_align Franck Bui-Huu2008-01-291-6/+3
* [MIPS] tlbex.c: cleanup include filesFranck Bui-Huu2008-01-291-6/+0
* [MIPS] tlbex.c: Cleanup __init usages.Franck Bui-Huu2008-01-291-49/+49
* [MIPS] R4000/R4400 daddiu erratum workaroundMaciej W. Rozycki2008-01-291-12/+30
* [MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.Ralf Baechle2008-01-291-8/+6
* [MIPS] Revert "[MIPS] tlbex.c: Cleanup __init usage."Ralf Baechle2007-10-131-48/+48
* [MIPS] tlbex.c: Cleanup __init usage.Franck Bui-Huu2007-10-121-48/+48
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-121-47/+47
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-121-5/+5
* [MIPS] tlbex: Size optimize code by declaring a few functions inline.Ralf Baechle2007-10-121-4/+4
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-121-0/+2
* [MIPS] Workaround for 4Kc machine check exceptionMaciej W. Rozycki2007-09-141-1/+25
* [MIPS] TLB: Fix instruction bitmasksThiemo Seufer2007-09-101-2/+2
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-3/+5
* [MIPS] tlbex: use __maybe_unusedDavid Rientjes2007-05-111-18/+18
* [MIPS] Load modules to CKSEG0 if CONFIG_BUILD_ELF64=nAtsushi Nemoto2006-11-301-0/+55
* [MIPS] 16K & 64K page size fixesRalf Baechle2006-11-011-3/+10
* Attack of "the the"s in archMatt LaPlante2006-10-031-1/+1
* [MIPS] Print out TLB handler assembly for debugging.Thiemo Seufer2006-07-131-88/+71
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-0/+1
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-0/+1
* [MIPS] MT: Improved multithreading support.Ralf Baechle2006-04-191-20/+63
* [MIPS] Fix vectored interrupt support in TLB exception handler generator.Ralf Baechle2006-04-191-2/+2
* [MIPS] Remove CONFIG_BUILD_ELF64.Ralf Baechle2006-03-211-13/+0
* [MIPS] Scatter a bunch of __init over tlbex.c.Ralf Baechle2006-03-091-17/+17
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-0/+1
* R4600 v2.0 needs a nop before tlbp.Thiemo Seufer2005-10-291-0/+2
* Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle2005-10-291-0/+1
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-291-20/+10
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-0/+1
* Detect the 34K.Ralf Baechle2005-10-291-0/+1
* Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle2005-10-291-1/+1
* Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki2005-10-291-1/+6
* Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki2005-10-291-1/+8
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