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* MIPS: Drop mmap_sem in pagefault oom pathAkinobu Mita2009-08-031-0/+1
| | | | | | | | Fix the pagefault oom path which does not drop mm->mmap_sem. This was introduced by commit c7c1e3846bac1e4b8a8941f6a194812e28b0a519 Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Eleminate filenames from commentsRalf Baechle2009-08-031-1/+5
| | | | | | | | | | They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
* [PATCH] MIPS: Cavium: Move swapped comments to their rightful place.Ralf Baechle2009-08-031-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* headers: smp_lock.h reduxAlexey Dobriyan2009-07-121-1/+0
| | | | | | | | | | | | | * Remove smp_lock.h from files which don't need it (including some headers!) * Add smp_lock.h to files which do need it * Make smp_lock.h include conditional in hardirq.h It's needed only for one kernel_locked() usage which is under CONFIG_PREEMPT This will make hardirq.h inclusion cheaper for every PREEMPT=n config (which includes allmodconfig/allyesconfig, BTW) Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle2009-06-2411-0/+11
| | | | | | | | | Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Move FAULT_FLAG_xyz into handle_mm_fault() callersLinus Torvalds2009-06-211-1/+1
| | | | | | | | | | This allows the callers to now pass down the full set of FAULT_FLAG_xyz flags to handle_mm_fault(). All callers have been (mechanically) converted to the new calling convention, there's almost certainly room for architectures to clean up their code and then add FAULT_FLAG_RETRY when that support is added. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: TLB support for hugetlbfs.David Daney2009-06-172-12/+196
| | | | | | | | | | | | | | | | | The TLB handlers need to check for huge pages and give them special handling. Huge pages consist of two contiguous sub-pages of physical memory. * Loading entrylo0 and entrylo1 need to be handled specially. * The page mask must be set for huge pages and then restored after writing the TLB entries. * The PTE for huge pages resides in the PMD, we halt traversal of the tables there. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support files for hugetlbfs.David Daney2009-06-172-0/+102
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unused parameters from iPTE_LW.David Daney2009-06-171-14/+14
| | | | | | | | The l parameter to iPTE_LW() is unused. Remove it and from some of its callers as well. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove dead case label.David Daney2009-06-171-1/+0
| | | | | | | | | CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch. This label in the switch statement is dead code, so we remove it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-171-1/+2
| | | | | | | | | | Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fold the TLB refill at the vmalloc path if possible.David Daney2009-06-171-24/+49
| | | | | | | | | | | | | Try to fold the 64-bit TLB refill handler opportunistically at the beginning of the vmalloc path so as to avoid splitting execution flow in half and wasting cycles for a branch required at that point then. Resort to doing the split if either of the newly created parts would not fit into its designated slot. Original-patch-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace some magic numbers with symbolic values in tlbex.cDavid Daney2009-06-171-8/+26
| | | | | | | | | | | The logic used to split the r4000 refill handler is liberally sprinkled with magic numbers. We attempt to explain what they are and normalize them against a new symbolic value (MIPS64_REFILL_INSNS). CC: David VomLehn <dvomlehn@cisco.com> Reviewed-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support 64-byte D-cache line sizeKevin Cernekee2009-06-171-0/+12
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Pass struct device to plat_dma_addr_to_phys()Kevin Cernekee2009-06-171-7/+8
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add size and direction arguments to plat_unmap_dma_mem()Kevin Cernekee2009-06-171-4/+4
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 64-bit: Fix system lockup.Greg Ungerer2009-05-203-10/+5
| | | | | | | | | | | | | | | | The address range size calculation inside local_flush_tlb_kernel_range() is being truncated by a too small size variable holder on 64-bit systems. The truncated size can result in an erroneous tlbsize check that means we sit spinning inside a loop trying to flush a hige number of TLB entries. This is for all intents and purposes a system hang. Fix by using an appropriately sized valiable to hold the size. [Ralf: Greg's original patch submission identified the issue and fixed one instance in tlb-r4k.c but there there were several more. For consistency I also modified tlb-r3k.c even though that file is only used on 32-bit.] Signed-off-by: Greg Ungerer <gerg@snapgear.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix highmem.Ralf Baechle2009-05-142-32/+19
| | | | | | | | | | | | | | | | | | | | | Commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 (kernel.org) rsp. b3594a089f1c17ff919f8f78505c3f20e1f6f8ce (linux-mips.org): > From: Chris Dearman <chris@mips.com> > Date: Wed, 19 Sep 2007 00:58:24 +0100 > Subject: [PATCH] [MIPS] Allow setting of the cache attribute at run time. > > Slightly tacky, but there is a precedent in the sparc archirecture code. introduces the variable _page_cachable_default, which defaults to zero and. is used to create the prototype PTE for __kmap_atomic in arch/mips/mm/init.c:kmap_init before initialization in arch/mips/mm/c-r4k.c:coherency_setup, so the default value of 0 will be used as the CCA of kmap atomic pages which on many processors is not a defined CCA value and may result in writes to kmap_atomic pages getting corrupted. Debugged by Jon Fraser (jfraser@broadcom.com). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Synchronize dma_map_page and dma_map_singleAtsushi Nemoto2009-05-141-18/+1
| | | | | | | | | | Synchronize dma_map_page/dma_unmap_page and dma_map_single/dma_unmap_single. This will reduce unnecessary writebacks and invalidates. [Ralf: make dma_unmap_page an inline function.] Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Print the actual detected I-cache associativity on bootup.Ralf Baechle2009-05-141-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP32: Two symbols can become staticDmitri Vorobiev2009-05-141-2/+2
| | | | | | | | | | | | The file arch/mips/mm/sc-rm7k.c needlessly defines two global symbols: rm7k_sc_ops rm7k_tcache_enabled This patch makes these symbols static. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mm: use debug_kmap_atomicAkinobu Mita2009-04-011-0/+2
| | | | | | | | | | | | | Use debug_kmap_atomic in kmap_atomic, kmap_atomic_pfn, and iomap_atomic_prot_pfn. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: Alchemy: MIPS hazard workarounds are not required.Manuel Lauss2009-03-301-1/+1
| | | | | | | | | | | | | | The Alchemy manuals state: "All pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute correctly. Therefore, it is not necessary to pad legacy MIPS hazards (such as load delay slots and coprocessor accesses) with NOPs." Run-tested on Au12x0, without any ill effects. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: unify CPU model constants.Manuel Lauss2009-03-302-19/+6
| | | | | | | | | | | | | | | | | This patch removes the various CPU_AU1??? model constants in favor of a single CPU_ALCHEMY one. All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts of the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already; and finally nothing else in-tree depends on those any more. Should a new variant with slightly different "company options" and/or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use BUG_ON() where possible.Ralf Baechle2009-03-303-14/+7
| | | | | | | Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which missed a few places. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: VR5500: Enable prefetchShinya Kuribayashi2009-03-231-1/+1
| | | | | Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix oops in dma_unmap_page on not coherent mips platformsJan Nikitenko2009-03-231-1/+1
| | | | | | | | | | | dma_cache_wback_inv() expects virtual address, but physical was provided due to translation via plat_dma_addr_to_phys(). If replaced with dma_addr_to_virt(), page fault oops from dma_unmap_page() is gone on au1550 platform. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: NEC VR5500 processor support fixupShinya Kuribayashi2009-03-112-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CVE-2009-0029: Enable syscall wrappers.Ralf Baechle2009-02-271-2/+3
| | | | | | | Thanks to David Daney helping with debugging and testing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Port "mm: invoke oom-killer from page fault" from UML / x86Ralf Baechle2009-01-301-15/+6
| | | | | | Original commit 1c0fe6e3bda0464728c23c8d84aa47567e8b716c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Avoid destructive invalidation on partial cachelines.Ralf Baechle2009-01-301-1/+21
| | | | | | See discussion e9c3a7c20901051031y528d0d31r18d44c5096c59e0@mail.gmail.com. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Only write c0_framemask on CPUs which have this register.Ralf Baechle2009-01-111-1/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Adjust the dma-common.c platform hooks.David Daney2009-01-111-15/+10
| | | | | | | | | We add a dev parameter to plat_unmap_dma_mem(), and hooks for plat_dma_supported() and plat_extra_sync_for_device() which should be nop changes for all existing targets. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney2009-01-111-0/+1
| | | | | | | | | | Expand the case statement for build_tlb_write_entry so that it does the right thing on Cavium CPU variants. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook up Cavium OCTEON in arch/mips.David Daney2009-01-111-0/+1
| | | | | | | | | | Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-111-0/+6
| | | | | | | | | Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney2009-01-112-0/+377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
* MIPS: Add missing calls to plat_unmap_dma_mem.David Daney2008-12-121-0/+3
| | | | | | | | dma_free_noncoherent() and dma_free_coherent() are missing calls to plat_unmap_dma_mem(). This patch adds them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP22: Make indy_sc_ops variable staticDmitri Vorobiev2008-11-201-1/+1
| | | | | | | | | The indy_sc_ops variable in arch/mips/mm/sc-ip22.c is needlessly defined global, and this patch makes it static. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi2008-10-271-0/+1
| | | | | | | | | | | | We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't unmap the memory for dma_sync*.David Daney2008-10-271-2/+0
| | | | | | | | | We were getting away with this for so long only because the only platform with a non-empty plat_unmap_dma_mem() doesn't call dma_sync_sg_for_cpu() and dma_sync_sg_for_device() from its commonly used drivers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX39xx: Add missing local_flush_icache_range initializationAtsushi Nemoto2008-09-051-0/+1
| | | | | | | | | Commmit 59e39ecd933ba49eb6efe84cbfa5597a6c9ef18a ("Fix WARNING: at kernel/smp.c:290") introduced local_flush_icache_range but lacks initialization for some TX39 case. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-055-9/+18
| | | | | | | | | | | trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] tlb-r4k: Nuke broken paranoia error test.Ralf Baechle2008-07-301-4/+0
| | | | | | | | | Bug originally found and reported by Julia Lawall <julia@diku.dk>. I decieded that the whole error check was mostly useless paranoia and should be discarded. It would only ever trigger if r3k_have_wired_reg has a wrong value. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: use generic show_mem()Johannes Weiner2008-07-262-38/+1
| | | | | | | | | | | | | | | | | | | Remove arch-specific show_mem() in favor of the generic version. This also removes the following redundant information display: - pages in swapcache, printed by show_swap_cache_info() where show_mem() calls show_free_areas(), which calls show_swap_cache_info(). And show_mem() does now actually print something on configurations with multiple nodes. Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* dma-mapping: add the device argument to dma_mapping_error()FUJITA Tomonori2008-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add per-device dma_mapping_ops support for CONFIG_X86_64 as POWER architecture does: This enables us to cleanly fix the Calgary IOMMU issue that some devices are not behind the IOMMU (http://lkml.org/lkml/2008/5/8/423). I think that per-device dma_mapping_ops support would be also helpful for KVM people to support PCI passthrough but Andi thinks that this makes it difficult to support the PCI passthrough (see the above thread). So I CC'ed this to KVM camp. Comments are appreciated. A pointer to dma_mapping_ops to struct dev_archdata is added. If the pointer is non NULL, DMA operations in asm/dma-mapping.h use it. If it's NULL, the system-wide dma_ops pointer is used as before. If it's useful for KVM people, I plan to implement a mechanism to register a hook called when a new pci (or dma capable) device is created (it works with hot plugging). It enables IOMMUs to set up an appropriate dma_mapping_ops per device. The major obstacle is that dma_mapping_error doesn't take a pointer to the device unlike other DMA operations. So x86 can't have dma_mapping_ops per device. Note all the POWER IOMMUs use the same dma_mapping_error function so this is not a problem for POWER but x86 IOMMUs use different dma_mapping_error functions. The first patch adds the device argument to dma_mapping_error. The patch is trivial but large since it touches lots of drivers and dma-mapping.h in all the architecture. This patch: dma_mapping_error() doesn't take a pointer to the device unlike other DMA operations. So we can't have dma_mapping_ops per device. Note that POWER already has dma_mapping_ops per device but all the POWER IOMMUs use the same dma_mapping_error function. x86 IOMMUs use device argument. [akpm@linux-foundation.org: fix sge] [akpm@linux-foundation.org: fix svc_rdma] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix bnx2x] [akpm@linux-foundation.org: fix s2io] [akpm@linux-foundation.org: fix pasemi_mac] [akpm@linux-foundation.org: fix sdhci] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix sparc] [akpm@linux-foundation.org: fix ibmvscsi] Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: Avi Kivity <avi@qumranet.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2008-07-162-4/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (54 commits) [MIPS] Remove mips_machtype for LASAT machines [MIPS] Remove mips_machtype from EMMA2RH machines [MIPS] Remove mips_machtype from ARC based machines [MIPS] MTX-1 flash partition setup move to platform devices registration [MIPS] TXx9: cleanup and fix some sparse warnings [MIPS] TXx9: rename asm-mips/mach-jmr3927 to asm-mips/mach-tx39xx [MIPS] remove machtype for group Toshiba [MIPS] separate rbtx4927_time_init() and rbtx4937_time_init() [MIPS] separate rbtx4927_arch_init() and rbtx4937_arch_init() [MIPS] txx9_cpu_clock setup move to rbtx4927_time_init() [MIPS] txx9_board_vec set directly without mips_machtype [MIPS] IP22: Add platform device for Indy volume buttons [MIPS] cmbvr4133: Remove support [MIPS] remove wrppmc_machine_power_off() [MIPS] replace inline assembler to cpu_wait() [MIPS] IP22/28: Add platform devices for HAL2 [MIPS] TXx9: Update and merge defconfigs [MIPS] TXx9: Make single kernel can support multiple boards [MIPS] TXx9: Update defconfigs [MIPS] TXx9: Reorganize PCI code ...
| * [MIPS] Make two functions staticDmitri Vorobiev2008-07-152-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following routines uasm_rel_highest() uasm_rel_higher() are needlessly defined global. This patch makes them static. Compile-tested using a customized config for the Malta board. Booting the same board up to the shell prompt was also successful with this patch applied. Spotted by sparse. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'generic-ipi' into generic-ipi-for-linusIngo Molnar2008-07-151-9/+9
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/powerpc/Kconfig arch/s390/kernel/time.c arch/x86/kernel/apic_32.c arch/x86/kernel/cpu/perfctr-watchdog.c arch/x86/kernel/i8259_64.c arch/x86/kernel/ldt.c arch/x86/kernel/nmi_64.c arch/x86/kernel/smpboot.c arch/x86/xen/smp.c include/asm-x86/hw_irq_32.h include/asm-x86/hw_irq_64.h include/asm-x86/mach-default/irq_vectors.h include/asm-x86/mach-voyager/irq_vectors.h include/asm-x86/smp.h kernel/Makefile Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * smp_call_function: get rid of the unused nonatomic/retry argumentJens Axboe2008-06-261-9/+9
| | | | | | | | | | | | | | | | It's never used and the comments refer to nonatomic and retry interchangably. So get rid of it. Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
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