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* MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.Ralf Baechle2014-05-231-1/+0
* MIPS: mm: Fix broken microMIPS kernel regression.Steven J. Hill2014-05-142-4/+7
* mips: export flush_icache_rangeKees Cook2014-04-191-2/+2
* MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen2014-03-313-2/+63
* MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin2014-03-311-1/+1
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-262-0/+2
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-262-5/+5
* MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin2014-03-261-0/+11
* MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras2014-03-261-2/+4
* MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin2014-03-261-0/+47
* MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras2014-03-261-1/+11
* MIPS: Add cases for CPU_P5600James Hogan2014-03-263-0/+3
* MIPS: Coherent Processing System SMP implementationPaul Burton2014-03-261-1/+1
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-063-1/+4
* MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras2014-03-061-3/+8
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-01-3117-38/+55
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| * mips: delete non-required instances of include <linux/init.h>Paul Gortmaker2014-01-2412-12/+0
| * MIPS: improve checks for noncoherent DMAFelix Fietkau2014-01-221-0/+2
| * MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-222-0/+2
| * MIPS: Add support for FTLBsLeonid Yegoshin2014-01-221-7/+22
| * MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin2014-01-221-6/+12
| * MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-223-0/+3
| * MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras2014-01-222-8/+1
| * MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved valueMarkos Chandras2014-01-221-8/+16
* | MIPS: fix blast_icache32 on loongson2Aaro Koskinen2014-01-151-0/+7
* | MIPS: fix case mismatch in local_r4k_flush_icache_range()Huacai Chen2014-01-151-2/+2
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* Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2013-11-121-3/+2
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| * Merge tag 'v3.12-rc4' into sched/coreIngo Molnar2013-10-097-27/+48
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| * | sched: Extract the basic add/sub preempt_count modifiersPeter Zijlstra2013-09-251-3/+2
* | | MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-293-119/+139
* | | MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXTJayachandran C2013-10-292-35/+57
* | | MIPS: Remove unnecessary platform dma helper functionsFelix Fietkau2013-10-291-3/+1
* | | MIPS: Move definition of SMP processor id register to header fileJayachandran C2013-10-291-50/+6
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* | MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcachesYoichi Yuasa2013-10-021-0/+2
* | MIPS: mm: Move some checks out of 'for' loop in DMA operationsJayachandran C2013-09-251-8/+4
* | MIPS: 74K/1074K: Correct erratum workaround.Maciej W. Rozycki2013-09-181-8/+18
* | MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki2013-09-181-5/+6
* | MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-177-10/+17
* | MIPS: Fix accessing to per-cpu data when flushing the cacheRalf Baechle2013-09-171-0/+5
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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-09-136-8/+32
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| * Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-061-3/+3
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| | * MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible codeJerin Jacob2013-09-061-2/+2
| * | Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-051-0/+1
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| | * MIPS: Export copy_from_user_page() (needed by lustre)Geert Uytterhoeven2013-09-051-0/+1
| * | Merge branch '3.11-fixes' into mips-for-linux-nextRalf Baechle2013-09-041-1/+2
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| | * MIPS: Fix get_user_page_fast() for mips with cache aliasKamal Dasu2013-08-261-1/+2
| * | MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000Jim Quinlan2013-09-041-6/+10
| * | MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.David Daney2013-08-261-0/+14
| * | MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.David Daney2013-08-261-0/+2
| * | MIPS: tlbex: Guard tlbmiss_handler_setup_pgdTony Wu2013-08-261-0/+2
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