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* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-182-5/+9
* [MIPS] Scatter a bunch of __init over tlbex.c.Ralf Baechle2006-03-091-17/+17
* [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle2006-02-281-5/+11
* [MIPS] Sibyte: #if CONFIG_* doesn't fly.Ralf Baechle2006-02-211-1/+1
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-142-151/+23
* [MIPS] Support /proc/kcore for MIPSDaniel Jacobowitz2006-02-071-0/+16
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-072-7/+5
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-101-2/+2
* [PATCH] mips: setup_zero_pages count 1Hugh Dickins2005-12-121-2/+2
* [MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.Ralf Baechle2005-12-011-1/+1
* [PATCH] mm: init_mm without ptlockHugh Dickins2005-10-301-3/+1
* SB1 cache exception handling.Andrew Isaacson2005-10-292-8/+51
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-0/+1
* Fix zero length sys_cacheflushAtsushi Nemoto2005-10-291-0/+2
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-291-16/+17
* Fix wrong comment.Ralf Baechle2005-10-291-1/+1
* Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle2005-10-291-2/+2
* Don't copy SB1 cache error handler to uncached memory.Ralf Baechle2005-10-291-1/+0
* Fix stale comment in c-sb1.c.Andrew Isaacson2005-10-291-1/+1
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-295-54/+44
* Use R4000 TLB routines for SB1 also.Ralf Baechle2005-10-292-386/+1
* Sync c-tx39.c with c-r4k.c.Atsushi Nemoto2005-10-291-4/+5
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-292-1/+2
* Minor code cleanup.Thiemo Seufer2005-10-291-15/+15
* R4600 v2.0 needs a nop before tlbp.Thiemo Seufer2005-10-291-0/+2
* Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer2005-10-291-38/+8
* More .set push/pop.Thiemo Seufer2005-10-291-2/+2
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-292-7/+10
* Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle2005-10-291-0/+1
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-294-29/+13
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-0/+1
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-292-5/+3
* Mark a few variables __read_mostly.Ralf Baechle2005-10-291-1/+7
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-291-0/+1
* Detect the 34K.Ralf Baechle2005-10-291-0/+1
* Define kmap_atomic_pfn() for MIPS.Ralf Baechle2005-10-291-0/+19
* Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle2005-10-291-1/+1
* Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle2005-10-294-6/+6
* Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki2005-10-291-1/+6
* Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki2005-10-291-12/+3
* Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki2005-10-291-1/+8
* Fix a diagnostic message.Maciej W. Rozycki2005-10-291-1/+1
* Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki2005-10-291-9/+9
* Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki2005-10-291-40/+30
* Fill R3k load delay slots properly.Maciej W. Rozycki2005-10-291-0/+3
* Only dump instructions actually emitted.Maciej W. Rozycki2005-10-291-7/+7
* Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.Thiemo Seufer2005-10-291-23/+29
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-292-25/+10
* Arrested for multiple offences of header file inclusion.Ralf Baechle2005-10-291-1/+1
* Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer2005-10-292-45/+63
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