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* tree-wide: fix assorted typos all over the placeAndré Goddard Rosa2009-12-047-7/+7
* MIPS: O32: Fix ppollArnaud Patard2009-11-021-1/+1
* MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin2009-11-021-1/+1
* MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss2009-11-021-8/+26
* MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto2009-11-021-1/+1
* MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli2009-11-021-0/+3
* MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le2009-11-021-2/+1
* MIPS: Avoid potential hazard on Context registerRalf Baechle2009-11-022-0/+4
* MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney2009-11-021-36/+178
* MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney2009-11-021-4/+6
* MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle2009-11-021-0/+1
* MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan2009-11-022-4/+31
* MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan2009-11-021-3/+13
* MIPS: GIC: Random fixes and enhancements.Chris Dearman2009-11-025-293/+142
* MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman2009-11-021-3/+4
* MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens2009-11-022-17/+7
* MIPS: SPRAM: Clean up support code a littleChris Dearman2009-11-023-10/+12
* MIPS: 1004K: Enable SPRAM support.Ralf Baechle2009-11-021-0/+1
* MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle2009-11-021-0/+13
* MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle2009-11-021-2/+1
* MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman2009-11-021-1/+1
* MIPS: Fix machine check exception in kmap_coherent()Kevin Cernekee2009-11-022-3/+7
* MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.Ralf Baechle2009-11-021-2/+1
* MIPS: AR7: register watchdog device only if enabled in hw configurationFlorian Fainelli2009-11-022-1/+11
* MIPS: BCM63xx: Prepare for watchdog supportFlorian Fainelli2009-11-022-1/+38
* MIPS: BCM63xx: Make bcm63xx_uart_register an initfuncFlorian Fainelli2009-11-023-10/+1
* MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoCFlorian Fainelli2009-11-021-0/+2
* MIPS: BCM63xx: Fix soft-reset lockup on BCM6345Florian Fainelli2009-11-021-1/+3
* MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove.Ralf Roesch2009-11-021-1/+2
* MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-026-6/+6
* MIPS: 64-bit: Fix o32 lookup_dcookie syscallWu Zhangjin2009-11-022-1/+7
* MIPS: VPE: Remove stray unlock_kernel.Ralf Baechle2009-11-021-2/+0
* MIPS: Add IRQF_TIMER flag for timer interruptsWu Zhangjin2009-11-027-7/+7
* MIPS: Loongson: Remove redundant local_irq_disable()Wu Zhangjin2009-11-021-1/+0
* MIPS: IP27: Fix buildRalf Baechle2009-11-021-2/+2
* MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.Ralf Baechle2009-11-021-8/+1
* MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.cDavid Daney2009-11-021-2/+3
* MIPS: Don't write ones to reserved entryhi bits.Ralf Baechle2009-11-021-5/+5
* MIPS: Extend COMMAND_LINE_SIZERalf Baechle2009-11-021-1/+1
* MIPS: Avoid spurious make includecheck messageRalf Baechle2009-09-301-2/+2
* MIPS: VPE: Get rid of BKL.Ralf Baechle2009-09-302-42/+50
* MIPS: VPE: Fix build after the credential changes a while ago.Ralf Baechle2009-09-301-10/+23
* MIPS: Excite: Get rid of BKL.Ralf Baechle2009-09-301-2/+0
* MIPS: Sibyte: Get rid of BKL.Ralf Baechle2009-09-301-18/+15
* MIPS: BCM63xx: Add PCMCIA & Cardbus support.Maxime Bizon2009-09-304-1/+162
* MIPS: MSP71xx: request_irq() failure ignored in msp_pcibios_config_access()Roel Kluin2009-09-301-1/+4
* MIPS: Decrease size of au1xxx_dbdma_pm_regs[][]Roel Kluin2009-09-301-5/+3
* MIPS: SMP: Inline arch_send_call_function_{single_ipi,ipi_mask}Ralf Baechle2009-09-302-15/+13
* MIPS: SMP: Fix build.Ralf Baechle2009-09-302-2/+2
* MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.Kevin Cernekee2009-09-301-0/+5
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