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* powerpc: Call do_page_fault() with interrupts offBenjamin Herrenschmidt2012-03-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently turn interrupts back to their previous state before calling do_page_fault(). This can be annoying when debugging as a bad fault will potentially have lost some processor state before getting into the debugger. We also end up calling some generic code with interrupts enabled such as notify_page_fault() with interrupts enabled, which could be unexpected. This changes our code to behave more like other architectures, and make the assembly entry code call into do_page_faults() with interrupts disabled. They are conditionally re-enabled from within do_page_fault() in the same spot x86 does it. While there, add the might_sleep() test in the case of a successful trylock of the mmap semaphore, again like x86. Also fix a bug in the existing assembly where r12 (_MSR) could get clobbered by C calls (the DTL accounting in the exception common macro and DISABLE_INTS) in some cases. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- v2. Add the r12 clobber fix
* powerpc/32: Pass device tree address as u64 to machine_initScott Wood2011-09-201-10/+3
| | | | | | | | | | | | | | | | | | u64 is used rather than phys_addr_t to keep things simple, as this is called from assembly code. Update callers to pass a 64-bit address in r3/r4. Other unused register assignments that were once parameters to machine_init are dropped. For FSL BookE, look up the physical address of the device tree from the effective address passed in r3 by the loader. This is required for situations where memory does not start at zero (due to AMP or IOMMU-less virtualization), and thus the IMA doesn't start at zero, and thus the device tree effective address does not equal the physical address. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove second definition of STACK_FRAME_OVERHEADStephen Rothwell2010-11-291-0/+1
| | | | | | | | | Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that is ASSEMBER safe, we can just include that instead of going via asm-offsets.h. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Use SPRG2 and DAR registers to stash r11 and cr.Joakim Tjernlund2010-04-071-13/+36
| | | | | | | | | This avoids storing these registers in memory. CPU6 errata will still use the old way. Remove some G2 leftover accesses from 2.4 Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Don't touch ACCESSED when no SWAP.Joakim Tjernlund2010-04-071-2/+4
| | | | | | | | | Only the swap function cares about the ACCESSED bit in the pte. Do not waste cycles updateting ACCESSED when swap is not compiled into the kernel. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Avoid testing for kernel space in ITLB Miss.Joakim Tjernlund2010-04-071-0/+4
| | | | | | | | Only modules will cause ITLB Misses as we always pin the first 8MB of kernel memory. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Optimze TLB Miss handlersJoakim Tjernlund2010-04-071-8/+3
| | | | | | | | This removes a couple of insn's from the TLB Miss handlers whithout changing functionality. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Fix user space TLB walk in dcbX fixupJoakim Tjernlund2010-01-151-2/+2
| | | | | | | | | The newly added fixup for buggy dcbX insn's has a bug that always trigger a kernel TLB walk so a user space dcbX insn will cause a Kernel Machine Check if it hits DTLB error. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Always pin kernel instruction TLBJoakim Tjernlund2010-01-151-4/+4
| | | | | | | | | | Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: DTLB Miss cleanupJoakim Tjernlund2009-12-091-6/+11
| | | | | | | Use symbolic constant for PRESENT and avoid branching. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Remove DIRTY pte handling in DTLB Error.Joakim Tjernlund2009-12-091-96/+0
| | | | | | | | There is no need to do set the DIRTY bit directly in DTLB Error. Trap to do_page_fault() and let the generic MM code do the work. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Restore _PAGE_WRITETHRUJoakim Tjernlund2009-12-091-0/+8
| | | | | | | | | | | 8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Add missing Guarded setting in DTLB Error.Joakim Tjernlund2009-12-091-3/+10
| | | | | | | | only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Fixup DAR from buggy dcbX instructions.Joakim Tjernlund2009-12-091-4/+143
| | | | | | | | | | This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Tag DAR with 0x00f0 to catch buggy instructions.Joakim Tjernlund2009-12-091-1/+14
| | | | | | | | | | | dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/8xx: Update TLB asm so it behaves as linux mm expects.Joakim Tjernlund2009-12-091-48/+51
| | | | | | | | | | | | | | | | | | Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED. Get rid of _PAGE_HWWRITE too. Pros: - I/D TLB Miss never needs to write to the linux pte. - _PAGE_ACCESSED is only set on TLB Error fixing accounting - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly when a page has been made dirty. - Proper RO/RW mapping of user space. - Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?) - kernel RO/user NA support. Cons: - A few more instructions in the TLB Miss routines. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Use names rather than numbers for SPRGs (v2)Benjamin Herrenschmidt2009-08-201-6/+7
| | | | | | | | | | | | | | | | | | | | | | The kernel uses SPRG registers for various purposes, typically in low level assembly code as scratch registers or to hold per-cpu global infos such as the PACA or the current thread_info pointer. We want to be able to easily shuffle the usage of those registers as some implementations have specific constraints realted to some of them, for example, some have userspace readable aliases, etc.. and the current choice isn't always the best. This patch should not change any code generation, and replaces the usage of SPRN_SPRGn everywhere in the kernel with a named replacement and adds documentation next to the definition of the names as to what those are used for on each processor family. The only parts that still use the original numbers are bits of KVM or suspend/resume code that just blindly needs to save/restore all the SPRGs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: convert to use __HEAD and HEAD_TEXT macros.Tim Abbott2009-04-261-1/+2
| | | | | | | | | | | This has the consequence of changing the section name use for head code from ".text.head" to ".head.text". Since this commit changes all users in the architecture, this change should be harmless. Signed-off-by: Tim Abbott <tabbott@mit.edu> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [POWERPC] 8xx: fix swapVitaly Bordug2008-03-071-1/+29
| | | | | | | | | | | | | | This makes swap routines operate correctly on the ppc_8xx based machines. Code has been revalidated on mpc885ads (8M sdram) with recent kernel. Based on patch from Yuri Tikhonov <yur@emcraft.com> to do the same on arch/ppc instance. Recent kernel's size makes swap feature very important on low-memory platforms, those are actually non-operable without it. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Work around CPU15 erratum.Scott Wood2007-10-041-0/+6
| | | | | | | | | | | | | The CPU15 erratum on MPC8xx chips can cause incorrect code execution under certain circumstances, where there is a conditional or indirect branch in the last word of a page, with a target in the last cache line of the next page. This patch implements one of the suggested workarounds, by forcing a TLB miss whenever execution crosses a page boundary. This is done by invalidating the pages before and after the one being loaded into the TLB in the ITLB miss handler. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 8xx: Fix CONFIG_PIN_TLB.Scott Wood2007-10-041-2/+2
| | | | | | | | 1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Remove cmd_line from head*.SStephen Rothwell2007-09-191-8/+0
| | | | | | | It is just a C char array, so declare it thusly. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Fix modpost warnings from head*.S on ppc32Kumar Gala2007-09-141-6/+3
| | | | | | | | | | | | | | | We get warnings like the following from the various ppc32 head*.S files: WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base') Added a .text.head section simliar to what other architectures do since modpost already excludes this from its warnings. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [PATCH] powerpc: trivial: modify comments to refer to new location of filesJon Mason2006-02-101-2/+0
| | | | | | | | | This patch removes all self references and fixes references to files in the now defunct arch/ppc64 tree. I think this accomplises everything wanted, though there might be a few references I missed. Signed-off-by: Jon Mason <jdmason@us.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Rename asm offset TRAP to _TRAP for 32-bitPaul Mackerras2005-10-281-1/+1
| | | | | | ... for consistency with 64-bit. Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: merge idle_power4.S and trapc.sStephen Rothwell2005-10-011-21/+21
| | | | | | | | | | | | | Use idle_power4.S from ppc64 as we are not going to support 32 bit power4 in the merged tree. Merge ppc64 traps.c into powerpc traps.c: use ppc64 versions of exception routine names (as they don't have StudlyCaps) make all the versions if die() have the same prototype Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
* powerpc: Merge enough to start building in arch/powerpc.Paul Mackerras2005-09-261-0/+860
This creates the directory structure under arch/powerpc and a bunch of Kconfig files. It does a first-cut merge of arch/powerpc/mm, arch/powerpc/lib and arch/powerpc/platforms/powermac. This is enough to build a 32-bit powermac kernel with ARCH=powerpc. For now we are getting some unmerged files from arch/ppc/kernel and arch/ppc/syslib, or arch/ppc64/kernel. This makes some minor changes to files in those directories and files outside arch/powerpc. The boot directory is still not merged. That's going to be interesting. Signed-off-by: Paul Mackerras <paulus@samba.org>
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