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* [POWERPC] 4xx: Add 440SPe revA runtime detection to PCIeStefan Roese2007-12-231-8/+17
| | | | | | | | | | | | This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PCI-E Link setup improvementsBenjamin Herrenschmidt2007-12-232-89/+133
| | | | | | | | | | | | | | This improves the way the 4xx PCI-E code handles checking for a link and adds explicit testing of CRS result codes on config space accesses. This should make it more reliable. Also, bridges with no link are now still created, though config space accesses beyond the root complex are filtered. This is one step toward eventually supporting hotplug. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI Express supportBenjamin Herrenschmidt2007-12-233-18/+1226
| | | | | | | | | | | | | | | | | | | | | | | | | This adds to the previous 2 patches the support for the 4xx PCI Express cells as found in the 440SPe revA, revB and 405EX. Unfortunately, due to significant differences between these, and other interesting "features" of those pieces of HW, the code isn't as simple as it is for PCI and PCI-X and some of the functions differ significantly between the 3 implementations. Thus, not only this code can only support those 3 implementations for now and will refuse to operate on any other, but there are added ifdef's to avoid the bloat of building a fairly large amount of code on platforms that don't need it. Also, this code currently only supports fully initializing root complex nodes, not endpoint. Some more code will have to be lifted from the arch/ppc implementation to add the endpoint support, though it's mostly differences in memory mapping, and the question on how to represent endpoint mode PCI in the device-tree is thus open. Many thanks to Stefan Roese for testing & fixing up the 405EX bits ! Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI 2.x supportBenjamin Herrenschmidt2007-12-232-1/+198
| | | | | | | | This adds to the previous patch the support for the 4xx PCI 2.x bridges. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI-X supportBenjamin Herrenschmidt2007-12-233-0/+448
| | | | | | | | | | | This adds base support code for the 4xx PCI-X bridge. It also provides placeholders for the PCI and PCI-E version but they aren't supported with this patch. The bridges are configured based on device-tree properties. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Merge branch 'linux-2.6'Paul Mackerras2007-12-211-2/+1
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| * [POWRPC] CPM2: Eliminate section mismatch warning in cpm2_reset().Scott Wood2007-12-141-2/+1
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] pci32: Add flags modifying the PCI code behaviourBenjamin Herrenschmidt2007-12-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds to the 32 bits PCI code some flags, replacing the old pci_assign_all_busses global, that allow us to control various aspects of the PCI probing, such as whether to re-assign all resources or not, or to not try to assign anything at all. This also adds the flag x86 already has to avoid ISA alignment on bridges that don't have ISA forwarding enabled (no legacy devices on the top level bus) and sets it for PowerMacs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] arch/powerpc/: Spelling fixesjoe@perches.com2007-12-202-2/+2
| | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] pasemi: Implement MSI supportOlof Johansson2007-12-204-1/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement MSI support for PA Semi PWRficient platforms. MSI is done through a special range of sources on the openpic controller, and they're unfortunately breaking the usual concepts of how sources are programmed: * The source is calculated as 512 + the value written into the MSI register * The vector for this source is added to the source and reported through IACK This means that for simplicity, it makes much more sense to just set the vector to 0 for the source, since that's really the vector we expect to see from IACK. Also, the affinity/priority registers will affect 16 sources at a time. To avoid most (simple) users from being limited by this, allocate 16 sources per device but use only one. This means that there's a total of 32 sources. If we get usage scenarions that need more sources, the allocator should probably be revised to take an alignment argument and size, not just do natural alignment. Finally, since I'm already touching the MPIC names on pasemi, rename the base one from the somewhat odd " PAS-OPIC " to "PASEMI-OPIC". Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] MPIC: Minor optimization of ipi handlerOlof Johansson2007-12-201-8/+7
| | | | | | | | | | | | | | | | | | | | Optimize MPIC IPIs, by passing in the IPI number as the argument to the handler, since all we did was translate it back based on which mpic the interrupt came though on (and that was always the primary mpic). Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] qe: add function qe_clock_source()Timur Tabi2007-12-141-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Add function qe_clock_source() which takes a string containing the name of a QE clock source (as is typically found in device trees) and returns the matching enum qe_clock value. Update booting-without-of.txt to indicate that the UCC properties rx-clock and tx-clock are deprecated and replaced with rx-clock-name and tx-clock-name, which use strings instead of numbers to indicate QE clock sources. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Move CPM command handling into the cpm driversJochen Friedrich2007-12-142-0/+53
| | | | | | | | | | | | | | | | | | | | | | This patch moves the CPM command handling into commproc.c for CPM1 and cpm2_common.c. This is yet another preparation to get rid of drivers accessing the CPM via the global cpmp. Signed-off-by: Jochen Friedrich <jochen@scram.de> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
* | [POWERPC] Add support for PORTA and PORTB odr registersJochen Friedrich2007-12-141-3/+16
| | | | | | | | | | | | | | | | | | PORTA and PORTB have odr registers, as well. However, the PORTB odr register is only 16bit. Signed-off-by: Jochen Friedrich <jochen@scram.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
* | [POWERPC] ipic: ack only for edge interruptsLi Yang2007-12-122-74/+45
| | | | | | | | | | | | | | | | | | | | Only external interrupts in edge detect mode support ack operation. Therefore, in most cases ack is not needed. The patch makes ipic ack only when it's needed. This could boost over all system performance. Signed-off-by: Li Yang <leoli@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] FSL: enet device tree cleanupsKumar Gala2007-12-121-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Removed address fields in ethernet nodes * Removed #address-cells, #size-cells from gianfar nodes * Added cell-index to gianfar and ucc ethernet nodes * Added enet[0..3] labels * Renamed compatible node for gianfar mdio to "fsl,gianfar-mdio" * Removed device_type = "mdio" The matching for gianfar mdio still supports the old "mdio"/"gianfar" combo but it is now considered deprecated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] FSL: I2C device tree cleanupsKumar Gala2007-12-121-5/+3
| | | | | | | | | | | | | | | | * Removed device_type = "i2c" * Added missing second I2C controller on MPC8548 CDS, MPC8544 DS * Added #address-cells, #size-cells, and cell-index where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] QE: change qe_setbrg() to take an enum qe_clock instead of an integerTimur Tabi2007-12-111-5/+9
| | | | | | | | | | | | | | | | | | qe_setbrg() currently takes an integer to indicate the BRG number. Change that to take an enum qe_clock instead, since this enum is intended to represent clock sources. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] ipic: add new interrupts introduced by new chipLi Yang2007-12-112-9/+136
| | | | | | | | | | | | | | | | These interrupts are introduced by the latest Freescale SoC such as MPC837x. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Clean out asm/of_{platform, device}.h from sysdev/Jon Loeliger2007-12-062-4/+5
| | | | | | | | | | | | | | | | Convert #include of asm/of_{platform, device}.h into linux/of_{platform,device}.h for remaining arch/powerpc files. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Add missing spaces in printk formatsjoe@perches.com2007-12-031-1/+1
|/ | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'for-2.6.24' of ↵Paul Mackerras2007-11-201-1/+17
|\ | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge
| * [POWERPC] 4xx: UIC add mask_ack callbackValentine Barshak2007-11-191-1/+17
| | | | | | | | | | | | | | | | | | | | This adds uic_mask_ack_irq() callback to PowerPC 4xx uic code to avoid kernel crash. It is used for edge-triggered interrupts by handle_uic_irq(). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] cpm: Fix a couple minor issues in cpm_common.c.Scott Wood2007-11-091-3/+1
|/ | | | | | | | A debugging printk is removed, and a comment is fixed to match the code. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fix mv643xx_pci sysfs .read and .write functionsDale Farnsworth2007-11-081-4/+6
| | | | | | | | | | | | | Commit 91a69029 introduced an additional parameter to the .read and .write methods for sysfs binary attributes. Two mv64x60_pci functions were missed in that patch, resulting in these errors: /cache/git/linux-2.6/arch/powerpc/sysdev/mv64x60_pci.c:77: warning: initialization from incompatible pointer type /cache/git/linux-2.6/arch/powerpc/sysdev/mv64x60_pci.c:78: warning: initialization from incompatible pointer type Add the missing "struct bin_attribute *" parameter. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] i8259: Add disable methodAurelien Jarno2007-11-081-0/+1
| | | | | | | | | | | | Since commit 76d2160147f43f982dfe881404cfde9fd0a9da21, the NE2000 card is not working anymore on PPC and POWERPC and produces WATCHDOG timeouts. The patch below fixes that the same way it has been done on x86, x86_64 and MIPS. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] bestcomm: Restrict bus prefetch bugfix to original mpc5200 silicon.Grant Likely2007-10-211-3/+6
| | | | | | Only the MPC5200 needs this bug fix. MPC5200B is okay. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* Merge branch 'for-2.6.24' of git://git.secretlab.ca/git/linux-2.6-mpc52xx ↵Paul Mackerras2007-10-1719-0/+2535
|\ | | | | | | into merge
| * [POWERPC] bestcomm: GenBD task supportSylvain Munaut2007-10-176-0/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the microcode for the GenBD task and the associated support code. This is a generic task that copy data to/from a hardware FIFO. This is currently locked to 32bits wide access but could be extended as needed. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [POWERPC] bestcomm: FEC task supportSylvain Munaut2007-10-176-0/+509
| | | | | | | | | | | | | | | | | | | | | | This is the microcode for the FEC task and the associated support code. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [POWERPC] bestcomm: ATA task supportSylvain Munaut2007-10-175-0/+267
| | | | | | | | | | | | | | | | | | | | | | This is the microcode for the ATA task and the associated support code. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [POWERPC] bestcomm: core bestcomm support for Freescale MPC5200Sylvain Munaut2007-10-178-0/+1310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the core of the BestComm API for the Freescale MPC5200(b). The BestComm engine is a microcode-controlled / tasks-based DMA used by several of the onchip devices. Setting up the tasks / memory allocation and all common low level functions are handled by this patch. The specifics details of each tasks and their microcode are split-out in separate patches. This is not the official API, but a much cleaner one. (hopefully) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | [POWERPC] Add missing semicolon for fsl_pci.cTony Li2007-10-161-1/+1
|/ | | | | Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use dcr_host_t.base in dcr_unmap()Michael Ellerman2007-10-151-2/+2
| | | | | | | | | With the base stored in dcr_host_t, there's no need for callers to pass the dcr_n into dcr_unmap(). In fact this removes the possibility of them passing the incorrect value, which would then be iounmap()'ed. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* Add dcr_host_t.base in dcr_read()/dcr_write()Michael Ellerman2007-10-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we can save them the trouble and do it in dcr_read()/dcr_write(). As some background to why we just went through all this jiggery-pokery, benh sayeth: Initially the goal of the dcr_read/dcr_write routines was to operate like mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx hardware, indirect DCR access is a pain (goes through a table of instructions) and it's useful to have the compiler resolve an absolute DCR inline. We decided that wasn't worth the API bastardisation since most places where absolute DCR values are used are low level 4xx-only code which may as well continue using mfdcr/mtdcr, while the new API is designed for device "instances" that can exist on 4xx and Axon type platforms and may be located at variable DCR offsets. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* missed bio_endio() in axonramAl Viro2007-10-121-2/+2
| | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pciValentine Barshak2007-10-121-2/+4
| | | | | | | | Add 64-bit physical address support to setup_indirect_pci(). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'virtex-for-2.6.24' of ↵Josh Boyer2007-10-111-1/+1
|\ | | | | | | git://git.secretlab.ca/git/linux-2.6-virtex into for-2.6.24-4xx
| * [POWERPC] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernelsGrant Likely2007-10-101-1/+1
| | | | | | | | | | | | | | dcr.c is an arch/powerpc only thing. Compiling ppc405 arch/ppc kernels throws warnings without this change. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | [POWERPC] Move of_platform_driver initialisations: arch/powerpcStephen Rothwell2007-10-112-5/+9
|/ | | | | | | | | | We no longer initialise the name and owner fields of the of_platform_driver, but use the fields of the embedded device_driver's name field instead. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] spi: Support non-QE processorsPeter Korsgaard2007-10-081-0/+4
| | | | | | | On non-QE processors (mpc831x/mpc834x) the SPI clock is the SoC clock. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QE: pario - support for MPC85xx layoutAnton Vorontsov2007-10-081-0/+3
| | | | | | | | 8 bytes padding required to match MPC85xx registers layout. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascadingAnton Vorontsov2007-10-081-22/+7
| | | | | | | | | | | | | | | | | | | | | | | | | set_irq_chained_handler overwrites MPIC's handle_irq function (handle_fasteoi_irq) thus MPIC never gets eoi event from the cascaded IRQ. This situation hangs MPIC on MPC8568E. To solve this problem efficiently, QEIC needs pluggable handlers, specific to the underlaying interrupt controller. Patch extends qe_ic_init() function to accept low and high interrupt handlers. To avoid #ifdefs, stack of interrupt handlers specified in the header file and functions are marked 'static inline', thus handlers are compiled-in only if actually used (in the board file). Another option would be to lookup for parent controller and automatically detect handlers (will waste text size because of never used handlers, so this option abolished). qe_ic_init() also changed in regard to support multiplexed high/low lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic() handler implemented appropriately. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 85xx/86xx: refactor RSTCR reset codeKumar Gala2007-10-082-0/+39
| | | | | | | | | On the majority of 85xx & 86xx we have a register that's ability to assert HRESET_REQ to reset the board. We refactored that code so it can be shared between both platforms into fsl_soc.c and removed all the duplication in each platform directory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] FSL: Access PCIe LTSSM register with correct sizeKumar Gala2007-10-081-2/+2
| | | | | | | The LTSSM register is actual 32-bits wide so we should be doing a dword access. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Treat 8610 PCIe host bridge as transparentJason Jin2007-10-081-0/+1
| | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] qe: miscellaneous code improvements and fixes to the QE libraryTimur Tabi2007-10-086-282/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes numerous miscellaneous code improvements to the QE library. 1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type() (every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all callers of ucc_set_type() accordingly. 2. Remove the unused enum ucc_pram_initial_offset. 3. Refactor qe_setbrg(), also implement work-around for errata QE_General4. 4. Several printk() calls were missing the terminating \n. 5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where appropriate. 6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed with the wrong value. 7. Add the protocol type to struct us_info and updated ucc_slow_init() to use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED. 8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx() 9. Add several macros in qe.h (mostly for slow UCC support, but also to standardize some naming convention) and remove several unused macros. 10. Update ucc_geth.c to use the new macros. 11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol to use when initializing the UCC in ucc_slow_init(). 12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since these are the real names of the registers. 13. Use the setbits, clrbits, and clrsetbits where appropriate. 14. Refactor ucc_set_qe_mux_rxtx(). 15. Remove all instances of 'volatile'. 16. Simplify get_cmxucr_reg(); 17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[]. 18. Updated struct ucc_geth because struct ucc_fast is not padded any more. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] MPC8568E-MDS: add support for ds1374 rtcAnton Vorontsov2007-10-041-0/+1
| | | | | | | | | | | | MPC8568E-MDS have DS1374 chip on the I2C bus, thus let's use it. This patch also adds #address-cells and #size-cells to the I2C controllers nodes. p.s. DS1374 rtc class driver is in the -mm tree, its name is rtc-rtc-class-driver-for-the-ds1374.patch. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: fix uninitialized i2c_board_info structureAnton Vorontsov2007-10-041-2/+1
| | | | | | | | | i2c_board_info used semi-initialized, causing garbage in the info->flags, and that, in turn, causes various symptoms of i2c malfunctioning, like PEC mismatches. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] cpm: Describe multi-user ram in its own device node.Scott Wood2007-10-043-24/+181
| | | | | | | | | | | | | | | | | | | | | The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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