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* RISC-V: defconfig: Drop redundant SBI HVC and earlyconPalmer Dabbelt2022-04-011-2/+0
| | | | | | | | As of 3938d5a2f936 ("riscv: default to CONFIG_RISCV_SBI_V01=n") we no longer default to enabling SBI-0.1 support, so these dependent configs no longer have any effect. Remove them to avoid clutter. Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* RISC-V: Enable profiling by defaultAnup Patel2022-03-311-0/+1
| | | | | | | | | Let us enable profiling by default in RV32 and RV64 defconfigs so that we can use RISC-V PMU drivers on various RISC-V platforms. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* RISC-V CPU Idle SupportPalmer Dabbelt2022-03-311-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series adds RISC-V CPU Idle support using SBI HSM suspend function. The RISC-V SBI CPU idle driver added by this series is highly inspired from the ARM PSCI CPU idle driver. Special thanks Sandeep Tripathy for providing early feeback on SBI HSM support in all above projects (RISC-V SBI specification, OpenSBI, and Linux RISC-V). * palmer/riscv-idle: RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine dt-bindings: Add common bindings for ARM and RISC-V idle states cpuidle: Add RISC-V SBI CPU idle driver cpuidle: Factor-out power domain related code from PSCI domain driver RISC-V: Add SBI HSM suspend related defines RISC-V: Add arch functions for non-retentive suspend entry/exit RISC-V: Rename relocate() and make it global RISC-V: Enable CPU_IDLE drivers
| * RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machineAnup Patel2022-03-101-0/+1
| | | | | | | | | | | | | | | | | | We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test SBI HSM Supend on QEMU. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: Enable CPU_IDLE driversAnup Patel2022-03-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | We force select CPU_PM and provide asm/cpuidle.h so that we can use CPU IDLE drivers for Linux RISC-V kernel. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@vetanamicro.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* | riscv: defconfig: enable hugetlbfs optionMayuresh Chitale2022-02-231-0/+1
|/ | | | | | | | | Enabling hugetlbfs in the defconfigs to allow tuning KVM guest performance using huge pages. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* Merge tag 'riscv-for-linus-5.17-mw0' of ↵Linus Torvalds2022-01-191-7/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for the DA9063 as used on the HiFive Unmatched. - Support for relative extables, which puts us in line with other architectures and save some space in vmlinux. - A handful of kexec fixes/improvements, including the ability to run crash kernels from PCI-addressable memory on the HiFive Unmatched. - Support for the SBI SRST extension, which allows systems that do not have an explicit driver in Linux to reboot. - A handful of fixes and cleanups, including to the defconfigs and device trees. * tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits) RISC-V: Use SBI SRST extension when available riscv: mm: fix wrong phys_ram_base value for RV64 RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign riscv: errata: alternative: mark vendor_patch_func __initdata riscv: head: make secondary_start_common() static riscv: remove cpu_stop() riscv: try to allocate crashkern region from 32bit addressible memory riscv: use hart id instead of cpu id on machine_kexec riscv: Don't use va_pa_offset on kdump riscv: dts: sifive: fu540-c000: Fix PLIC node riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values riscv: dts: sifive: Group tuples in register properties riscv: dts: sifive: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Fix clock controller node riscv: dts: microchip: mpfs: Fix reference clock node riscv: dts: microchip: mpfs: Fix PLIC node riscv: dts: microchip: mpfs: Drop empty chosen node riscv: dts: canaan: Group tuples in interrupt properties ...
| * RISC-V: defconfigs: Remove redundant CONFIG_EFI=yPalmer Dabbelt2022-01-061-1/+0
| | | | | | | | | | | | | | | | | | We've always had CONFIG_EFI as "def_bool y" so this has always been redundant. It's removed by savedefconfig, so drop it to keep things clean. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Remove redundant CONFIG_POWER_RESETPalmer Dabbelt2022-01-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | As of ab7fbad0c7d7 ("riscv: Fix unmet direct dependencies built based on SOC_VIRT") we select CONFIG_POWER_RESET=y along with CONFIG_SOC_VIRT, which is already in defconfig. This make setting CONFIG_POWER_RESET in the defconfigs redundant, so remove it to remain consistent with savedefconfig. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Sort CONFIG_MMCPalmer Dabbelt2022-01-061-1/+1
| | | | | | | | | | | | | | | | | | This should have no functional change, it just sorts CONFIG_MMC the same way savedefconfig does. This only touches the rv64 defconfig because rv32_defconfig was already sorted correctly. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Sort CONFIG_PTP_1588_CLOCKPalmer Dabbelt2022-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | This should have no functional change, it just sorts CONFIG_PTP_1588_CLOCK the same way savedefconfig does. This only touches the rv64 defconfig because rv32_defconfig was already sorted correctly. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Sort CONFIG_SOC_POLARFIREPalmer Dabbelt2022-01-061-1/+1
| | | | | | | | | | | | | | | | This should have no functional change, it just sorts CONFIG_SOC_POLARFIRE the same way savedefconfig does. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Sort CONFIG_SYSFS_SYSCALLPalmer Dabbelt2022-01-061-1/+1
| | | | | | | | | | | | | | | | This should have no functional change, it just sorts CONFIG_SYSFS_SYSCALL the same way savedefconfig does. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Sort CONFIG_BPF_SYSCALLPalmer Dabbelt2022-01-061-1/+1
| | | | | | | | | | | | | | | | This should have no functional change, it just sorts CONFIG_BPF_SYSCALL the same way savedefconfig does. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| * RISC-V: defconfigs: Set CONFIG_FB=y, for FB consolePalmer Dabbelt2022-01-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | We have CONFIG_FRAMEBUFFER_CONSOLE=y in the defconfigs, but that depends on CONFIG_FB so it's not actually getting set. I'm assuming most users on real systems want a framebuffer console, so this enables CONFIG_FB to allow that to take effect. Fixes: 33c57c0d3c67 ("RISC-V: Add a basic defconfig") Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* | RISC-V: Enable KVM in RV64 and RV32 defconfigs as a moduleAnup Patel2021-11-191-0/+2
|/ | | | | | | | | Let's enable KVM RISC-V in RV64 and RV32 defconfigs as module so that it always built along with the default kernel image. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
* riscv: defconfig: enable DRM_NOUVEAUHeinrich Schuchardt2021-10-271-3/+4
| | | | | | | | | | | Both RADEON and NOUVEAU graphics cards are supported on RISC-V. Enabling the one and not the other does not make sense. As typically at most one of RADEON, NOUVEAU, or VIRTIO GPU support will be needed DRM drivers should be compiled as modules. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: defconfig: enable NLS_CODEPAGE_437, NLS_ISO8859_1Heinrich Schuchardt2021-09-111-0/+2
| | | | | | | | | | | | | | The EFI system partition uses the FAT file system. Many distributions add an entry in /etc/fstab for the ESP. We must ensure that mounting does not fail. The default code page for FAT is 437 (cf. CONFIG_FAT_DEFAULT_CODEPAGE). The default IO character set is "iso8859-1" (cf. CONFIG_NLS_ISO8859_1). So let's enable NLS_CODEPAGE_437 and NLS_ISO8859_1 in defconfig. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: defconfig: enable BLK_DEV_NVMEHeinrich Schuchardt2021-09-111-0/+2
| | | | | | | | | | | | | NVMe is a non-volatile storage media attached via PCIe. As NVMe has much higher throughput than other block devices like SATA it is a must have for RISC-V. Enable CONFIG_BLK_DEV_NVME. The HiFive Unmatched is a board providing M.2 slots for NVMe drives. Enable CONFIG_PCIE_FU740. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* block: remove CONFIG_DEBUG_BLOCK_EXT_DEVTChristoph Hellwig2021-08-241-1/+0
| | | | | | | | | This might have been a neat debug aid when the extended dev_t was added, but that time is long gone. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210824075216.1179406-3-hch@lst.de Signed-off-by: Jens Axboe <axboe@kernel.dk>
* RISC-V: Enable Microchip PolarFire ICICLE SoCAtish Patra2021-04-261-0/+4
| | | | | | | | | | Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* RISC-V: Enable CPU Hotplug in defconfigsAnup Patel2021-02-271-0/+1
| | | | | | | | The CPU hotplug support has been tested on QEMU, Spike, and SiFive Unleashed so let's enable it by default in RV32 and RV64 defconfigs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: defconfig: enable gpio support for HiFive UnleashedSagar Shrikant Kadam2021-01-141-0/+2
| | | | | | | | | Ethernet phy VSC8541-01 on HiFive Unleashed has its reset line connected to a gpio, so enable GPIO driver's required to reset the phy. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* RISC-V: Add EFI stub support.Atish Patra2020-10-021-0/+1
| | | | | | | | | | | | | | | Add a RISC-V architecture specific stub code that actually copies the actual kernel image to a valid address and jump to it after boot services are terminated. Enable UEFI related kernel configs as well for RISC-V. Signed-off-by: Atish Patra <atish.patra@wdc.com> Link: https://lore.kernel.org/r/20200421033336.9663-4-atish.patra@wdc.com [ardb: - move hartid fetch into check_platform_features() - use image_size not reserve_size - select ISA_C - do not use dram_base] Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: Add jump-label implementationEmil Renner Berthing2020-07-301-0/+1
| | | | | | | | | | Add jump-label implementation based on the ARM64 version and add CONFIG_JUMP_LABEL=y to the defconfigs. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Björn Töpel <bjorn.topel@gmail.com> Tested-by: Björn Töpel <bjorn.topel@gmail.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* Merge tag 'riscv-for-linus-5.7' of ↵Linus Torvalds2020-04-091-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: "This contains a handful of new features: - Partial support for the Kendryte K210. There are still a few outstanding issues that I have patches for, but I don't actually have a board to test them so they're not included yet. - SBI v0.2 support. - Fixes to support for building with LLVM-based toolchains. The resulting images are known not to boot yet. I don't anticipate a part two, but I'll probably have something early in the RCs to finish up the K210 support" * tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) riscv: create a loader.bin boot image for Kendryte SoC riscv: Kendryte K210 default config riscv: Add Kendryte K210 device tree riscv: Select required drivers for Kendryte SOC riscv: Add Kendryte K210 SoC support riscv: Add SOC early init support riscv: Unaligned load/store handling for M_MODE RISC-V: Support cpu hotplug RISC-V: Add supported for ordered booting method using HSM RISC-V: Add SBI HSM extension definitions RISC-V: Export SBI error to linux error mapping function RISC-V: Add cpu_ops and modify default booting method RISC-V: Move relocate and few other functions out of __init RISC-V: Implement new SBI v0.2 extensions RISC-V: Introduce a new config for SBI v0.1 RISC-V: Add SBI v0.2 extension definitions RISC-V: Add basic support for SBI v0.2 RISC-V: Mark existing SBI as 0.1 SBI. riscv: Use macro definition instead of magic number riscv: Add support to dump the kernel page tables ...
| * riscv: Delete CONFIG_SYSFS_SYSCALL from defconfigsDeepa Dinamani2020-03-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | According to init/Kconfig: "sys_sysfs is an obsolete system call no longer supported in libc. Note that disabling this option is more secure but might break compatibility with some systems." This syscall is not required for new architectures. Since the config defaults to 'y'. Set this to 'n' exlicitly. Signed-off-by: Deepa Dinamani <deepa.kernel@gmail.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* | RISC-V: Only select essential drivers for SOC_VIRT configAnup Patel2020-03-261-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The kconfig select causes build failues for SOC_VIRT config becaus we are selecting lot of VIRTIO drivers without selecting all required dependencies. Better approach is to only select essential drivers from SOC_VIRT config option and enable required VIRTIO drivers using defconfigs. Fixes: 759bdc168181 ("RISC-V: Add kconfig option for QEMU virt machine") Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* | RISC-V: Select Goldfish RTC driver for QEMU virt machineAnup Patel2020-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | We select Goldfish RTC driver using QEMU virt machine kconfig option to access RTC device on QEMU virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* | RISC-V: Select SYSCON Reboot and Poweroff for QEMU virt machineAnup Patel2020-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | The SYSCON Reboot and Poweroff drivers can be used on QEMU virt machine to reboot or poweroff the system hence we select these drivers using QEMU virt machine kconfig option. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* | RISC-V: Enable QEMU virt machine support in defconfigsAnup Patel2020-03-051-14/+1
|/ | | | | | | | | | | | | We have kconfig option for QEMU virt machine so let's enable it in RV32 and RV64 defconfigs. Also, we remove various VIRTIO configs from RV32 and RV64 defconfigs because these are now selected by QEMU virt machine kconfig option. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: defconfigs: enable more debugging optionsPaul Walmsley2019-11-231-0/+23
| | | | | | | | Enable more debugging options in the RISC-V defconfigs to help kernel developers catch problems with patches earlier in the development cycle. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
* riscv: defconfigs: enable debugfsPaul Walmsley2019-11-221-0/+1
| | | | | | debugfs is broadly useful, so enable it in the RISC-V defconfigs. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
* RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfigAnup Patel2019-09-191-0/+11
| | | | | | | | | | | This patch enables more VIRTIO drivers (such as console, rpmsg, 9p, rng, etc.) which are usable on KVM RISC-V Guest and Xvisor RISC-V Guest. Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alexander Graf <graf@amazon.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* riscv: defconfig: Update the defconfigAlistair Francis2019-08-141-0/+2
| | | | | | | | Update the defconfig: - Add CONFIG_HW_RANDOM=y and CONFIG_HW_RANDOM_VIRTIO=y to enable VirtIORNG when running on QEMU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* riscv: defconfig: align RV64 defconfig to the output of "make savedefconfig"Paul Walmsley2019-07-311-5/+5
| | | | | | | | Align the RV64 defconfig to the output of "make savedefconfig" to avoid unnecessary deltas for future defconfig patches. This patch should have no runtime functional impact. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* riscv: defconfig: enable SOC_SIFIVELoys Ollivier2019-07-011-5/+1
| | | | | | | | | | Enable SOC_SIFIVE so the default upstream config is bootable on the SiFive Unleashed Board. And have basic support for future boards based on the same SoC. Signed-off-by: Loys Ollivier <lollivier@baylibre.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> [paul.walmsley@sifive.com: updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERSAnup Patel2019-07-011-0/+2
| | | | | | | | | | | | | | | | | This patch enables NO_HZ_IDLE (idle dynamic ticks) and HIGH_RES_TIMERS (hrtimers) in RV32 and RV64 defconfigs. Both of the above options are enabled by default for architectures such as x86, ARM, and ARM64. The idle dynamic ticks helps use save power by stopping timer ticks when the system is idle whereas hrtimers is a much improved timer subsystem compared to the old "timer wheel" based system. This patch is tested on SiFive Unleashed board and QEMU Virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* RISC-V: defconfig: enable MMC & SPI for RISC-VAtish Patra2019-06-261-0/+5
| | | | | | | | | | | | | | | | Currently, riscv upstream defconfig doesn't let you boot through userspace if rootfs is on the SD card. Let's enable MMC & SPI drivers as well so that one can boot to the user space using default config in upstream kernel. While here, enable automatic mounting of devtmpfs to simplify kernel testing with minimal root filesystems. (pjw) Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> [paul.walmsley@sifive.com: mention the DEVTMPFS_MOUNT change in the patch description] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* RISC-V: defconfig: enable clocks, serial consoleKevin Hilman2019-06-111-0/+4
| | | | | | | | Enable PRCI clock driver and serial console by default, so the default upstream defconfig is bootable to a serial console. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=yPalmer Dabbelt2019-01-231-0/+1
| | | | | | This allows acceleration of cryptography inside QEMU. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: defconfig: Enable Generic PCIE by defaultAlistair Francis2019-01-231-1/+2
| | | | | | | | | | | Enable generic PCIe by default in the RISC-V defconfig, this allows us to use QEMU's PCIe support out of the box. CONFIG_RAS=y is automatically selected by generic PCIe, so it has been dropped from the defconfig. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Split out PCIE_XILINX and CRYPTO_DEV_VIRTIO] Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}Palmer Dabbelt2019-01-231-2/+2
| | | | | | | | eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") reorganized the PCI-related Kconfig entries and resulted in a diff in our defconfig. This simply removes the diff. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: defconfig: Enable RISC-V SBI earlycon supportAnup Patel2018-12-171-0/+1
| | | | | | | | | | This patch enables RISC-V SBI earlycon support in default defconfig so that we can use "earlycon=sbi" in kernel parameters for early debug prints. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: defconfig: Enable printk timestampsAnup Patel2018-11-131-0/+1
| | | | | | | | | | | | | | The printk timestamps are very useful information to visually see where kernel is spending time during boot. It also helps us see the timing of hotplug events at runtime. This patch enables printk timestamps in RISC-V defconfig so that we have it enabled by default (similar to other architectures such as x86_64, arm64, etc). Signed-off-by: Anup Patel <anup@brainfault.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: refresh defconfigAnup Patel2018-11-021-8/+8
| | | | | | | | | This patch updates defconfig using savedefconfig on Linux-4.19. It is intended to have no functional change. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* irqchip: add a SiFive PLIC driverChristoph Hellwig2018-08-131-0/+1
| | | | | | | | | | | | | | | | Add a driver for the SiFive implementation of the RISC-V Platform Level Interrupt Controller (PLIC). The PLIC connects global interrupt sources to the local interrupt controller on each hart. This driver is based on the driver in the RISC-V tree from Palmer Dabbelt, but has been almost entirely rewritten since, and includes many fixes from Atish Patra. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> [Binding update by Palmer] Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfigPalmer Dabbelt2018-06-111-0/+1
| | | | | | | The SBI exists on all RISC-V systems, so there's no reason not to compile this driver in. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Enable module support in defconfigZong Li2018-04-031-0/+2
| | | | | Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add a basic defconfigKarsten Merker2018-01-081-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a basic defconfig for the RISC-V architecture that enables enough kernel features to run a basic Linux distribution on qemu's "virt" board for native software development. Features include: - serial console - virtio block and network device support - VFAT and ext2/3/4 filesystem support - NFS client and NFS rootfs support - an assortment of other kernel features required for running systemd It also enables a number of drivers for physical hardware that target the "SiFive U500" SoC and the corresponding development platform. These include: - PCIe host controller support for the FPGA-based U500 development platform (PCIE_XILINX) - USB host controller support (OHCI/EHCI/XHCI) - USB HID (keyboard/mouse) support - USB mass storage support (bulk and UAS) - SATA support (AHCI) - ethernet drivers (MACB for a SoC-internal MAC block, microsemi ethernet phy, E1000E and R8169 for PCIe-connected external devices) - DRM and framebuffer console support for PCIe-connected Radeon graphics chips Signed-off-by: Karsten Merker <merker@debian.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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