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path: root/arch/riscv/include/asm/csr.h (follow)
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* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-0/+5
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| * RISC-V: Add SSTC extension CSR detailsAtish Patra2022-08-111-0/+5
* | RISC-V: KVM: Add support for Svpbmt inside Guest/VMAnup Patel2022-07-291-0/+16
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* Merge tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-05-311-0/+7
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| * riscv: compat: syscall: Add entry.S implementationGuo Ren2022-04-261-0/+7
* | RISC-V: KVM: Add Sv57x4 mode support for G-stageAnup Patel2022-05-201-0/+1
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* perf: RISC-V: Add support for SBI PMU and SscofpmfPalmer Dabbelt2022-03-221-1/+65
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| * RISC-V: Add sscofpmf extension supportAtish Patra2022-03-211-1/+7
| * RISC-V: Add CSR encodings for all HPMCOUNTERSAtish Patra2022-03-211-0/+58
* | riscv: mm: Set sv57 on defaultlyQinglin Pan2022-02-151-0/+1
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* riscv: Implement sv48 supportAlexandre Ghiti2022-01-201-2/+1
* RISC-V: Add hypervisor extension related CSR definesAnup Patel2021-10-041-0/+87
* riscv: Introduce alternative mechanism to apply errata solutionVincent Chen2021-04-261-0/+3
* RISC-V: Implement ASID allocatorAnup Patel2021-02-191-0/+6
* RISC-V: Remove N-extension related definesAnup Patel2020-05-041-3/+0
* riscv: set pmp configuration if kernel is running in M-modeGreentime Hu2020-02-181-0/+12
* riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley2020-01-051-9/+9
* riscv: clear the instruction cache and all registers when bootingChristoph Hellwig2019-11-181-0/+1
* riscv: read the hart ID from mhartid on bootDamien Le Moal2019-11-181-0/+1
* riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-10/+62
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-171-7/+25
* RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel2019-05-171-4/+17
* RISC-V: Use tabs to align macro values in asm/csr.hAnup Patel2019-05-171-38/+38
* RISC-V: add a definition for the SIE SEIE bitChristoph Hellwig2018-08-131-0/+1
* riscv: rename sptbr to satpChristoph Hellwig2018-01-311-7/+7
* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-081-4/+4
* RISC-V: Generic library routines and assemblyPalmer Dabbelt2017-09-271-0/+132
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