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path: root/arch/riscv/include/asm/sbi.h (follow)
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* RISC-V: Add defines for the SBI nested acceleration extensionAnup Patel2024-10-281-0/+120
* Merge tag 'riscv-for-linus-6.12-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-09-241-0/+1
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| * perf/riscv-sbi: Add platform specific firmware event handlingMayuresh Chitale2024-09-201-0/+1
* | riscv: Fix RISCV_ALTERNATIVE_EARLYAlexandre Ghiti2024-09-031-1/+19
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* riscv: Improve sbi_ecall() code generation by reordering argumentsAlexandre Ghiti2024-07-101-4/+6
* Merge patch series "riscv: Extension parsing fixes"Palmer Dabbelt2024-05-231-0/+2
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| * riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins2024-05-221-0/+2
* | Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-05-221-0/+4
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| * | riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland2024-04-291-0/+4
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* | RISC-V: Use the minor version mask while computing sbi versionAtish Patra2024-04-221-2/+2
* | RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic nameAtish Patra2024-04-221-1/+1
* | RISC-V: Add SBI PMU snapshot definitionsAtish Patra2024-04-221-0/+11
* | drivers/perf: riscv: Use BIT macro for shifting operationsAtish Patra2024-04-221-10/+10
* | RISC-V: Add FIRMWARE_READ_HI definitionAtish Patra2024-04-221-0/+1
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* Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-01-201-0/+19
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| * Merge patch series "RISC-V SBI debug console extension support"Palmer Dabbelt2024-01-111-0/+10
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| | * RISC-V: Add SBI debug console helper routinesAnup Patel2024-01-101-0/+5
| | * RISC-V: Add stubs for sbi_console_putchar/getchar()Anup Patel2024-01-101-0/+5
| * | riscv: sbi: Introduce system suspend supportAndrew Jones2024-01-111-0/+9
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* / RISC-V: Add SBI STA extension definitionsAndrew Jones2023-12-301-0/+17
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* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-101-3/+0
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| * riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2023-11-061-3/+0
* | RISC-V: Add defines for SBI debug console extensionAnup Patel2023-10-201-0/+7
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* RISC-V: Align SBI probe implementation with specAndrew Jones2023-04-291-1/+1
* RISC-V: Treat IPIs as normal Linux IRQsAnup Patel2023-04-081-2/+7
* RISC-V: Improve SBI PMU extension related definitionsAtish Patra2023-02-071-2/+5
* RISC-V: Cache SBI vendor valuesHeiko Stuebner2022-10-271-0/+5
* RISC-V: Improve SBI definitionsAtish Patra2022-08-111-2/+16
* RISC-V: Move counter info definition to sbi header fileAtish Patra2022-08-111-0/+14
* Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-03-251-0/+95
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| * RISC-V: Add RISC-V SBI PMU extension definitionsAtish Patra2022-03-211-0/+95
* | RISC-V: Add SBI HSM suspend related definesAnup Patel2022-03-111-5/+22
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* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-9/+10
* Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2022-01-191-0/+24
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| * RISC-V: Use SBI SRST extension when availableAnup Patel2022-01-111-0/+24
* | RISC-V: KVM: Add SBI HSM extension in KVMAtish Patra2022-01-061-0/+1
* | RISC-V: KVM: Add SBI v0.2 base extensionAtish Patra2022-01-061-0/+8
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* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-061-0/+3
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| * riscv: Add 3 SBI wrapper functions to get cpu manufacturer informationVincent Chen2021-04-261-0/+3
* | RISC-V: correct enum sbi_ext_rfence_fidHeinrich Schuchardt2021-03-101-2/+2
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* RISC-V: Add a non-void return for sbi v02 functionsAtish Patra2021-02-231-5/+5
* riscv: Cleanup sbi function stubs when RISCV_SBI disabledKefeng Wang2021-01-081-7/+3
* RISC-V: Add SBI HSM extension definitionsAtish Patra2020-03-311-0/+14
* RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-0/+2
* RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-0/+14
* RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-0/+2
* RISC-V: Add SBI v0.2 extension definitionsAtish Patra2020-03-311-0/+21
* RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-311-71/+68
* RISC-V: Mark existing SBI as 0.1 SBI.Atish Patra2020-03-311-19/+22
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-181-0/+2
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