Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | riscv: provide native clint access for M-mode | Christoph Hellwig | 2019-11-18 | 1 | -0/+2 |
* | riscv: add support for MMIO access to the timer registers | Christoph Hellwig | 2019-11-13 | 1 | -1/+2 |
* | riscv: implement remote sfence.i using IPIs | Christoph Hellwig | 2019-11-13 | 1 | -0/+3 |
* | riscv: poison SBI calls for M-mode | Christoph Hellwig | 2019-11-13 | 1 | -2/+3 |
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 2019-06-05 | 1 | -9/+1 |
* | riscv: fix sbi_remote_sfence_vma{,_asid}. | Gary Guo | 2019-05-17 | 1 | -7/+12 |
* | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 2017-09-27 | 1 | -0/+100 |