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path: root/arch/riscv/include/asm/tlbflush.h (follow)
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* riscv: add nommu supportChristoph Hellwig2019-11-181-3/+9
* riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley2019-10-141-4/+0
* riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-051-30/+7
* riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-051-1/+0
* riscv: fix flush_tlb_range() end address for flush_tlb_page()Paul Walmsley2019-08-131-2/+9
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-231-3/+13
* riscv: use NULL instead of a plain 0Luc Van Oostenryck2018-06-071-1/+1
* RISC-V: Limit the scope of TLB shootdownsAndrew Waterman2018-01-311-8/+12
* riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-081-4/+0
* RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-011-0/+2
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| * RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-301-0/+2
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
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* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-271-0/+64