linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	riscv: mm: Fix incorrect ASID argument when flushing TLB	Dylan Jhong	2023-03-21	1	-0/+2
*	Revert "riscv: mm: notify remote harts about mmu cache updates"	Sergey Matyukevich	2023-03-10	1	-18/+0
*	riscv: mm: notify remote harts about mmu cache updates	Sergey Matyukevich	2022-12-09	1	-0/+18
*	riscv: fix build error when CONFIG_SMP is disabled	Bixuan Cui	2021-06-09	1	-0/+5
*	riscv: sifive: Apply errata "cip-1200" patch	Vincent Chen	2021-04-26	1	-1/+2
*	riscv: add nommu support	Christoph Hellwig	2019-11-18	1	-3/+9
*	riscv: tlbflush: remove confusing comment on local_flush_tlb_all()	Paul Walmsley	2019-10-14	1	-4/+0
*	riscv: move the TLB flush logic out of line	Christoph Hellwig	2019-09-05	1	-30/+7
*	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	2019-09-05	1	-1/+0
*	riscv: fix flush_tlb_range() end address for flush_tlb_page()	Paul Walmsley	2019-08-13	1	-2/+9
*	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	2019-06-05	1	-9/+1
*	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	2018-10-23	1	-3/+13
*	riscv: use NULL instead of a plain 0	Luc Van Oostenryck	2018-06-07	1	-1/+1
*	RISC-V: Limit the scope of TLB shootdowns	Andrew Waterman	2018-01-31	1	-8/+12
*	riscv: remove CONFIG_MMU ifdefs	Christoph Hellwig	2018-01-08	1	-4/+0
*	RISC-V: User-Visible Changes	Palmer Dabbelt	2017-12-01	1	-0/+2
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\| *	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	2017-11-30	1	-0/+2
* \|	RISC-V: `sfence.vma` orderes the instruction cache	Palmer Dabbelt	2017-11-28	1	-1/+4
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*	RISC-V: Atomic and Locking Code	Palmer Dabbelt	2017-09-27	1	-0/+64