linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	RISC-V: remove spin_unlock_wait()	Palmer Dabbelt	2017-11-28	1	-9/+0
*	RISC-V: `sfence.vma` orderes the instruction cache	Palmer Dabbelt	2017-11-28	1	-1/+4
*	RISC-V: Add READ_ONCE in arch_spin_is_locked()	Palmer Dabbelt	2017-11-28	1	-1/+1
*	RISC-V: __test_and_op_bit_ord should be strongly ordered	Palmer Dabbelt	2017-11-28	1	-1/+1
*	RISC-V: Remove smb_mb__{before,after}_spinlock()	Palmer Dabbelt	2017-11-28	1	-8/+0
*	RISC-V: Remove __smp_bp__{before,after}_atomic	Palmer Dabbelt	2017-11-28	1	-15/+0
*	RISC-V: Comment on why {,cmp}xchg is ordered how it is	Palmer Dabbelt	2017-11-28	1	-2/+7
*	RISC-V: Remove unused arguments from ATOMIC_OP	Palmer Dabbelt	2017-11-28	1	-47/+47
*	Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...	Linus Torvalds	2017-11-15	1	-14/+0
*	RISC-V: Build Infrastructure	Palmer Dabbelt	2017-09-27	1	-0/+61
*	RISC-V: User-facing API	Palmer Dabbelt	2017-09-27	15	-0/+710
*	RISC-V: Paging and MMU	Palmer Dabbelt	2017-09-27	7	-0/+910
*	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	2017-09-27	7	-0/+364
*	RISC-V: Task implementation	Palmer Dabbelt	2017-09-27	6	-0/+328
*	RISC-V: ELF and module implementation	Palmer Dabbelt	2017-09-27	3	-0/+150
*	RISC-V: Generic library routines and assembly	Palmer Dabbelt	2017-09-27	6	-0/+822
*	RISC-V: Atomic and Locking Code	Palmer Dabbelt	2017-09-27	10	-0/+1423
*	RISC-V: Init and Halt Code	Palmer Dabbelt	2017-09-27	3	-0/+162