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* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-131-1/+1
* riscv: Add SOC early init supportDamien Le Moal2020-04-031-0/+1
* riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-031-1/+1
* RISC-V: Support cpu hotplugAtish Patra2020-03-311-0/+1
* RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-0/+3
* RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-311-0/+2
* riscv: introduce interfaces to patch kernel codeZong Li2020-03-261-1/+3
* riscv: add nommu supportChristoph Hellwig2019-11-181-2/+1
* riscv: provide native clint access for M-modeChristoph Hellwig2019-11-181-0/+1
* riscv: cleanup the default power off implementationChristoph Hellwig2019-11-131-0/+1
* riscv: Add support for perf registers samplingMao Han2019-09-051-0/+1
* riscv: Add perf callchain supportMao Han2019-09-041-1/+2
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
* RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2019-03-271-3/+0
* Allow to disable FPU supportAlan Kao2018-10-231-1/+1
* Extract FPU context operations from entry.SAlan Kao2018-10-231-0/+1
* perf: riscv: preliminary RISC-V supportAlan Kao2018-06-041-0/+2
* RISC-V: Fixes to module loadingPalmer Dabbelt2018-04-031-0/+1
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| * RISC-V: Add sections of PLT and GOT for kernel moduleZong Li2018-04-031-0/+1
* | riscv/ftrace: Add dynamic function tracer supportAlan Kao2018-04-031-2/+3
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* riscv/ftrace: Add basic supportAlan Kao2018-01-311-0/+7
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-271-0/+33
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