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path: root/arch/riscv/kernel/cpufeature.c (follow)
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* Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt2024-01-101-0/+2
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| * riscv: add ISA extension parsing for ZacasClément Léger2024-01-101-0/+1
| * riscv: add ISA extension parsing for ZtsoClément Léger2024-01-101-0/+1
* | RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt2024-01-031-4/+0
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* riscv: add ISA extension parsing for ZfaClément Léger2023-12-131-0/+1
* riscv: add ISA extension parsing for Zvfh[min]Clément Léger2023-12-131-0/+2
* riscv: add ISA extension parsing for ZihintntlClément Léger2023-12-131-0/+1
* riscv: add ISA extension parsing for Zfh/Zfh[min]Clément Léger2023-12-131-0/+2
* riscv: add ISA extension parsing for vector cryptoClément Léger2023-12-131-0/+64
* riscv: add ISA extension parsing for scalar cryptoEvan Green2023-12-131-23/+95
* riscv: add ISA extension parsing for ZbcClément Léger2023-12-131-0/+1
* Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-101-13/+79
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| * RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-081-19/+77
| * riscv: don't probe unaligned access speed if already doneJisheng Zhang2023-11-051-0/+4
| * Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-1/+5
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| | * riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-0/+4
| | * riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger2023-11-011-1/+1
* | | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-081-5/+12
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| * | RISC-V: clarify the QEMU workaround in ISA parserTsukasa OI2023-11-011-3/+4
| * | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-211-0/+6
| * | RISC-V: Make zicbom/zicboz errors consistentAndrew Jones2023-09-211-2/+2
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* | RISC-V: Detect Zicond from ISA stringAnup Patel2023-10-121-0/+1
* | RISC-V: Detect Smstateen extensionMayuresh Chitale2023-10-121-0/+1
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* Merge patch series "RISC-V: Probe for misaligned access speed"Palmer Dabbelt2023-09-081-0/+104
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| * RISC-V: Probe for unaligned access speedEvan Green2023-09-011-0/+104
* | Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-09-011-181/+340
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| * | RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Conor Dooley2023-07-261-1/+13
| * | RISC-V: enable extension detection from dedicated propertiesConor Dooley2023-07-261-4/+74
| * | RISC-V: split riscv_fill_hwcap() in 3Conor Dooley2023-07-261-168/+177
| * | RISC-V: add single letter extensions to riscv_isa_extConor Dooley2023-07-261-0/+13
| * | RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Conor Dooley2023-07-261-21/+9
| * | RISC-V: shunt isa_ext_arr to cpufeature.cConor Dooley2023-07-261-0/+67
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* | Merge tag 'devicetree-header-cleanups-for-6.6' of git://git.kernel.org/pub/sc...Linus Torvalds2023-08-311-1/+0
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| * | riscv: Explicitly include correct DT includesRob Herring2023-08-281-1/+0
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* / RISC-V: Don't include Zicsr or Zifencei in I from ACPIPalmer Dabbelt2023-07-121-7/+2
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* Merge patch series "ISA string parser cleanups"Palmer Dabbelt2023-06-231-23/+85
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| * RISC-V: always report presence of extensions formerly part of the base ISAConor Dooley2023-06-211-0/+17
| * RISC-V: remove decrement/increment dance in ISA string parserConor Dooley2023-06-211-8/+6
| * RISC-V: rework comments in ISA string parserConor Dooley2023-06-211-11/+59
| * RISC-V: validate riscv,isa at boot, not during ISA string parsingConor Dooley2023-06-211-6/+6
| * RISC-V: simplify register width check in ISA string parsingConor Dooley2023-06-211-8/+7
* | Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Palmer Dabbelt2023-06-191-6/+10
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| * | RISC-V: Track ISA extensions per hartEvan Green2023-06-191-6/+12
| * | RISC-V: Add Zba, Zbs extension probingEvan Green2023-06-191-0/+2
* | | riscv: say disabling zicbom if no or bad riscv,cbom-block-size foundBen Dooks2023-06-141-2/+2
* | | Merge patch series "riscv: Add vector ISA support"Palmer Dabbelt2023-06-081-0/+25
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| * | riscv: Add prctl controls for userspace vector managementAndy Chiu2023-06-081-1/+8
| * | riscv: hwcap: change ELF_HWCAP to a functionAndy Chiu2023-06-081-0/+5
| * | riscv: Introduce riscv_v_vsize to record size of Vector contextGreentime Hu2023-06-081-0/+2
| * | riscv: Extending cpufeature.c to detect V-extensionGuo Ren2023-06-081-0/+11
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