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path: root/arch/riscv/kernel/cpufeature.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: Ensure isa-ext static keys are writableAndrew Jones2022-08-171-1/+1
* RISC-V: Add Sstc extension supportPalmer Dabbelt2022-08-111-0/+1
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| * RISC-V: Enable sstc extension parsing from DTAtish Patra2022-08-111-0/+1
* | arch/riscv: add Zihintpause supportDao Lu2022-08-111-0/+1
* | riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt2022-08-111-0/+24
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| * | riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner2022-07-291-0/+24
* | | RISC-V: Support for 64bit hartid on RV64 platformsPalmer Dabbelt2022-07-201-2/+4
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| * | riscv: cpu: Add 64bit hartid support on RV64Sunil V L2022-07-201-2/+4
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* | RISC-V: Some Svpbmt fixes and cleanupsPalmer Dabbelt2022-06-171-26/+11
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| * | riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner2022-06-171-22/+10
| * | riscv: drop cpufeature_apply_feature tracking variableHeiko Stuebner2022-06-171-4/+1
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* | riscv: switch has_fpu() to the unified static key mechanismJisheng Zhang2022-06-161-7/+0
* | riscv: introduce unified static key mechanism for ISA extensionsJisheng Zhang2022-06-161-0/+7
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* Merge tag 'bitmap-for-5.19-rc1' of https://github.com/norov/linuxLinus Torvalds2022-06-041-4/+3
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| * risc-v: replace bitmap_weight with bitmap_empty in riscv_fill_hwcap()Yury Norov2022-06-031-4/+3
* | riscv: add memory-type errata for T-HeadHeiko Stuebner2022-05-121-1/+6
* | riscv: add RISC-V Svpbmt extension supportHeiko Stuebner2022-05-121-1/+74
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* RISC-V: Add sscofpmf extension supportAtish Patra2022-03-211-0/+2
* RISC-V: Do no continue isa string parsing without correct XLENAtish Patra2022-03-171-0/+5
* RISC-V: Implement multi-letter ISA extension probing frameworkAtish Patra2022-03-171-6/+16
* RISC-V: Extract multi-letter extension names from "riscv, isa"Tsukasa OI2022-03-171-8/+27
* RISC-V: Minimal parser for "riscv, isa" stringsTsukasa OI2022-03-171-11/+61
* RISC-V: Correctly print supported extensionsTsukasa OI2022-03-171-3/+5
* riscv: Add __init section marker to some functions againJisheng Zhang2021-05-291-1/+1
* riscv: Turn has_fpu into a static key if FPU=yJisheng Zhang2021-05-261-2/+2
* RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2020-05-041-3/+80
* riscv: add missing header file includesPaul Walmsley2019-10-281-0/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-191-12/+1
* RISC-V: Assign hwcap as per comman capabilities.Atish Patra2019-03-041-19/+22
* riscv: use for_each_of_cpu_node iteratorJohan Hovold2019-02-121-2/+3
* riscv: add missing newlines to printk messagesJohan Hovold2019-02-121-4/+4
* RISC-V: Fix of_node_* refcountAtish Patra2018-12-211-0/+2
* RISC-V: properly determine hardware capsAndreas Schwab2018-10-311-3/+5
* riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-231-0/+8
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| * Auto-detect whether a FPU existsAlan Kao2018-10-231-0/+8
* | RISC-V: Mask out the F extension on systems without DPalmer Dabbelt2018-10-231-0/+7
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* RISC-V: User-facing APIPalmer Dabbelt2017-09-271-0/+61
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