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* Merge tag 'riscv-for-linus-5.8-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-06-1114-97/+96
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| * riscv: set the permission of vdso_data to read-onlyVincent Chen2020-06-111-2/+14
| * riscv: use vDSO common flow to reduce the latency of the time-related functionsVincent Chen2020-06-118-59/+51
| * riscv: fix build warning of missing prototypesZong Li2020-06-101-0/+1
| * RISC-V: Remove do_IRQ() functionAnup Patel2020-06-102-7/+3
| * irqchip: RISC-V per-HART local interrupt controller driverAnup Patel2020-06-102-32/+3
| * RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel2020-06-101-0/+16
| * RISC-V: self-contained IPI handling routineAnup Patel2020-06-102-8/+19
* | mmap locking API: use coccinelle to convert mmap_sem rwsem call sitesMichel Lespinasse2020-06-091-2/+2
* | mm: introduce include/linux/pgtable.hMike Rapoport2020-06-092-2/+2
* | mm: don't include asm/pgtable.h if linux/mm.h is already includedMike Rapoport2020-06-091-1/+0
* | kernel: rename show_stack_loglvl() => show_stack()Dmitry Safonov2020-06-091-7/+1
* | riscv: add show_stack_loglvl()Dmitry Safonov2020-06-091-3/+10
* | kallsyms/printk: add loglvl to print_ip_sym()Dmitry Safonov2020-06-091-1/+1
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* Merge tag 'riscv-for-linus-5.8-mw0' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-06-0510-21/+500
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| * riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structureYash Shah2020-05-211-0/+17
| * riscv: Use text_mutex instead of patch_lockZong Li2020-05-182-6/+20
| * riscv: Use NOKPROBE_SYMBOL() instead of __krpobes annotationZong Li2020-05-181-7/+14
| * riscv: Remove the 'riscv_' prefix of function nameZong Li2020-05-182-12/+12
| * riscv: Add SW single-step support for KDBVincent Chen2020-05-181-2/+177
| * riscv: Use the XML target descriptions to report 3 system registersVincent Chen2020-05-181-0/+15
| * riscv: Add KGDB supportVincent Chen2020-05-183-0/+206
| * RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt2020-05-181-1/+10
| * riscv: Allow device trees to be built into the kernelPalmer Dabbelt2020-05-183-0/+36
* | RISC-V: gp_in_global needs register keywordPalmer Dabbelt2020-05-211-1/+1
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* riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang2020-05-131-1/+1
* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-131-1/+1
* riscv: perf_event: Make some funciton staticKefeng Wang2020-05-111-4/+4
* riscv: force __cpu_up_ variables to put in data sectionZong Li2020-05-051-2/+2
* riscv: add Linux note to vdsoAndreas Schwab2020-05-042-1/+13
* RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2020-05-041-3/+80
* RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel2020-05-041-0/+2
* riscv: sbi: Fix undefined reference to sbi_shutdownKefeng Wang2020-04-221-5/+8
* riscv: sbi: Correct sbi_shutdown() and sbi_clear_ipi() exportKefeng Wang2020-04-221-2/+2
* riscv: fix vdso build with lldIlie Halip2020-04-221-3/+3
* RISC-V: stacktrace: Declare sp_in_global outside ifdefGuenter Roeck2020-04-211-2/+2
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-0918-206/+1679
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| * riscv: Add SOC early init supportDamien Le Moal2020-04-034-0/+36
| * riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-033-4/+395
| * RISC-V: Support cpu hotplugAtish Patra2020-03-314-1/+140
| * RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-316-3/+121
| * RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-1/+2
| * RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-314-21/+113
| * RISC-V: Move relocate and few other functions out of __initAtish Patra2020-03-312-72/+86
| * RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-4/+249
| * RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-23/+109
| * RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-312-2/+246
| * riscv: patch code by fixmap mappingZong Li2020-03-261-9/+4
| * riscv: introduce interfaces to patch kernel codeZong Li2020-03-262-1/+123
| * riscv: add macro to get instruction lengthZong Li2020-03-261-1/+2
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