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* riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen2019-09-201-1/+5
* RISC-V: Export kernel symbols for kvmAtish Patra2019-09-202-0/+2
* arch/riscv: disable excess harts before picking main boot hartXiang Wang2019-09-201-3/+5
* Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-09-178-35/+187
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| * riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig2019-09-051-0/+1
| * riscv: optimize send_ipi_singleChristoph Hellwig2019-09-051-1/+7
| * riscv: cleanup send_ipi_maskChristoph Hellwig2019-09-051-9/+7
| * riscv: refactor the IPI codeChristoph Hellwig2019-09-051-24/+31
| * riscv: Add support for perf registers samplingMao Han2019-09-052-0/+45
| * riscv: Add perf callchain supportMao Han2019-09-043-3/+98
| * riscv: Using CSR numbers to access CSRsBin Meng2019-08-303-8/+8
| * Merge tag 'common/for-v5.4-rc1/cpu-topology' into for-v5.4-rc1-branchPaul Walmsley2019-08-301-0/+3
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* | \ Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2019-09-161-0/+3
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| * \ \ Merge tag 'common/for-v5.4-rc1/cpu-topology' of git://git.kernel.org/pub/scm/...Will Deacon2019-08-141-0/+3
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| | * | RISC-V: Parse cpu topology during boot.Atish Patra2019-07-221-0/+3
* | | | riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley2019-09-141-2/+2
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* | | riscv: Correct the initialized flow of FP registerVincent Chen2019-08-141-2/+9
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* / riscv: Fix perf record without libelf supportMao Han2019-07-311-1/+1
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* Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-07-183-31/+43
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| * RISC-V: Add an Image header that boot loader can parse.Atish Patra2019-07-111-0/+32
| * RISC-V: Setup initial page tables in two stagesAnup Patel2019-07-092-12/+11
| * riscv: Remove gate area stubsAndy Lutomirski2019-07-011-19/+0
* | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2019-07-092-6/+7
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| * signal: Remove the task parameter from force_sig_faultEric W. Biederman2019-05-291-2/+2
| * signal: Explicitly call force_sig_fault on currentEric W. Biederman2019-05-291-1/+1
| * signal/riscv: Remove tsk parameter from do_trapEric W. Biederman2019-05-291-3/+4
| * signal: Remove task parameter from force_sigEric W. Biederman2019-05-271-1/+1
* | Merge tag 'spdx-5.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds2019-06-214-40/+4
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| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner2019-06-193-36/+3
* | | Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2019-06-171-0/+1
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| * | riscv: export pm_power_off againAndreas Schwab2019-06-111-0/+1
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-0520-180/+20
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-302-18/+2
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-9/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner2019-05-243-42/+3
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
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* Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2019-05-1914-125/+115
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| * RISC-V: Avoid using invalid intermediate translationsPalmer Dabbelt2019-05-171-2/+10
| * riscv: Support BUG() in kernel moduleVincent Chen2019-05-171-1/+1
| * riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen2019-05-171-3/+17
| * riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo2019-05-171-49/+0
| * RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-175-25/+25
| * RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel2019-05-171-12/+4
| * RISC-V: Fix minor checkpatch issues.Atish Patra2019-05-171-2/+2
| * RISC-V: Support nr_cpus command line option.Atish Patra2019-05-171-1/+9
| * RISC-V: Implement nosmp commandline option.Atish Patra2019-04-301-1/+11
| * RISC-V: Add RISC-V specific arch_match_cpu_phys_idAtish Patra2019-04-302-2/+7
| * riscv: vdso: drop unnecessary cc-ldoptionNick Desaulniers2019-04-301-1/+1
| * riscv: call pm_power_off from machine_halt / machine_power_offChristoph Hellwig2019-04-251-6/+9
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