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* Merge tag 'riscv-for-linus-5.8-mw0' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2020-06-0510-21/+500
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| * riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structureYash Shah2020-05-211-0/+17
| * riscv: Use text_mutex instead of patch_lockZong Li2020-05-182-6/+20
| * riscv: Use NOKPROBE_SYMBOL() instead of __krpobes annotationZong Li2020-05-181-7/+14
| * riscv: Remove the 'riscv_' prefix of function nameZong Li2020-05-182-12/+12
| * riscv: Add SW single-step support for KDBVincent Chen2020-05-181-2/+177
| * riscv: Use the XML target descriptions to report 3 system registersVincent Chen2020-05-181-0/+15
| * riscv: Add KGDB supportVincent Chen2020-05-183-0/+206
| * RISC-V: Skip setting up PMPs on trapsPalmer Dabbelt2020-05-181-1/+10
| * riscv: Allow device trees to be built into the kernelPalmer Dabbelt2020-05-183-0/+36
* | RISC-V: gp_in_global needs register keywordPalmer Dabbelt2020-05-211-1/+1
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* riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang2020-05-131-1/+1
* riscv: perf: RISCV_BASE_PMU should be independentKefeng Wang2020-05-131-1/+1
* riscv: perf_event: Make some funciton staticKefeng Wang2020-05-111-4/+4
* riscv: force __cpu_up_ variables to put in data sectionZong Li2020-05-051-2/+2
* riscv: add Linux note to vdsoAndreas Schwab2020-05-042-1/+13
* RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel2020-05-041-3/+80
* RISC-V: Export riscv_cpuid_to_hartid_mask() APIAnup Patel2020-05-041-0/+2
* riscv: sbi: Fix undefined reference to sbi_shutdownKefeng Wang2020-04-221-5/+8
* riscv: sbi: Correct sbi_shutdown() and sbi_clear_ipi() exportKefeng Wang2020-04-221-2/+2
* riscv: fix vdso build with lldIlie Halip2020-04-221-3/+3
* RISC-V: stacktrace: Declare sp_in_global outside ifdefGuenter Roeck2020-04-211-2/+2
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-0918-206/+1679
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| * riscv: Add SOC early init supportDamien Le Moal2020-04-034-0/+36
| * riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-033-4/+395
| * RISC-V: Support cpu hotplugAtish Patra2020-03-314-1/+140
| * RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-316-3/+121
| * RISC-V: Export SBI error to linux error mapping functionAtish Patra2020-03-311-1/+2
| * RISC-V: Add cpu_ops and modify default booting methodAtish Patra2020-03-314-21/+113
| * RISC-V: Move relocate and few other functions out of __initAtish Patra2020-03-312-72/+86
| * RISC-V: Implement new SBI v0.2 extensionsAtish Patra2020-03-311-4/+249
| * RISC-V: Introduce a new config for SBI v0.1Atish Patra2020-03-311-23/+109
| * RISC-V: Add basic support for SBI v0.2Atish Patra2020-03-312-2/+246
| * riscv: patch code by fixmap mappingZong Li2020-03-261-9/+4
| * riscv: introduce interfaces to patch kernel codeZong Li2020-03-262-1/+123
| * riscv: add macro to get instruction lengthZong Li2020-03-261-1/+2
| * riscv: add alignment for text, rodata and data sectionsZong Li2020-03-261-1/+4
| * riscv: move exception table immediately after RO_DATAZong Li2020-03-261-2/+4
| * RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt2020-03-031-82/+61
| * RISC-V: Stop relying on GCC's register allocator's hueristicsPalmer Dabbelt2020-03-032-5/+7
| * RISC-V: Stop putting .sbss in .sdataPalmer Dabbelt2020-03-031-1/+0
| * riscv: force hart_lottery to put in .sdata sectionZong Li2020-03-031-2/+6
* | Merge tag 'spdx-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds2020-04-032-0/+2
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| * | .gitignore: add SPDX License IdentifierMasahiro Yamada2020-03-252-0/+2
* | | Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-03-311-1/+1
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| * | | irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra2020-03-161-1/+1
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* | | riscv: fix the IPI missing issue in nommu modeGreentime Hu2020-03-191-1/+1
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* | riscv: fix seccomp reject syscall code pathTycho Andersen2020-03-052-14/+8
* | riscv: avoid the PIC offset of static percpu data in module beyond 2G limitsVincent Chen2020-03-031-0/+16
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* RISC-V: Don't enable all interrupts in trap_init()Anup Patel2020-02-181-2/+2
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