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path: root/arch/riscv/mm/tlbflush.c (follow)
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* RISC-V: Use IPIs for remote TLB flush when possibleAnup Patel2023-04-081-15/+78
* riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong2023-03-211-1/+1
* Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich2023-03-101-11/+17
* riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich2022-12-091-17/+11
* RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra2022-01-201-7/+2
* riscv: add ASID-based tlbflushing methodsGuo Ren2021-07-011-7/+40
* riscv: pass the mm_struct to __sbi_tlb_flush_rangeChristoph Hellwig2021-07-011-9/+6
* riscv: mm: add THP support on 64-bitNanyong Sun2021-05-221-0/+7
* riscv: mm: add param stride for __sbi_tlb_flush_rangeNanyong Sun2021-05-221-5/+5
* RISC-V: Issue a tlb page flush if possibleAtish Patra2019-10-291-1/+4
* RISC-V: Issue a local tlbflush if possible.Atish Patra2019-10-291-2/+17
* RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra2019-10-291-0/+3
* riscv: move the TLB flush logic out of lineChristoph Hellwig2019-09-051-0/+35