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* Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2019-07-184-68/+315
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| * RISC-V: Setup initial page tables in two stagesAnup Patel2019-07-091-52/+255
| * riscv: remove free_initrd_memChristoph Hellwig2019-07-041-5/+0
| * riscv: ccache: Remove unused variableYash Shah2019-07-041-4/+7
| * riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti2019-07-042-0/+46
| * RISC-V: Fix memory reservation in setup_bootmem()Anup Patel2019-07-011-7/+7
* | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2019-07-091-3/+3
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| * signal/riscv: Remove tsk parameter from do_trapEric W. Biederman2019-05-291-3/+3
* | riscv: mm: Fix code commentShihPo Hung2019-06-271-3/+0
* | Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2019-06-171-0/+13
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| * | riscv: mm: synchronize MMU after pte changeShihPo Hung2019-06-171-0/+13
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-053-27/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner2019-05-242-28/+2
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
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* Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2019-05-195-6/+310
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| * riscv: fix locking violation in page fault handlerAndreas Schwab2019-05-171-1/+2
| * RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah2019-05-172-0/+176
| * riscv: move switch_mm to its own fileGary Guo2019-05-172-0/+70
| * riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo2019-05-171-0/+61
| * RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-171-5/+1
* | riscv: switch over to generic free_initmem()Mike Rapoport2019-05-141-5/+0
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* RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systemsAnup Patel2019-04-101-0/+8
* RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2019-03-272-0/+34
* RISC-V: Free-up initrd in free_initrd_mem()Anup Patel2019-02-211-1/+2
* RISC-V: Implement compile-time fixed mappingsAnup Patel2019-02-211-0/+34
* RISC-V: Move setup_vm() to mm/init.cAnup Patel2019-02-211-0/+49
* RISC-V: Move setup_bootmem() to mm/init.cAnup Patel2019-02-211-0/+70
* riscv: fixup max_low_pfn with PFN_DOWN.Guo Ren2019-01-241-1/+2
* mm: remove include/linux/bootmem.hMike Rapoport2018-10-311-2/+1
* memblock: rename free_all_bootmem to memblock_free_allMike Rapoport2018-10-311-1/+1
* RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen2018-10-231-1/+1
* mm: convert return type of handle_mm_fault() caller to vm_fault_tSouptick Joarder2018-08-181-1/+2
* RISC-V: Add conditional macro for zone of DMA32Zong Li2018-07-041-0/+2
* Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-02-072-6/+10
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| * riscv: rename sptbr to satpChristoph Hellwig2018-01-311-0/+4
| * riscv: don't read back satp in paging_initChristoph Hellwig2018-01-311-2/+0
| * riscv: add ZONE_DMA32Christoph Hellwig2018-01-311-4/+6
* | Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2018-02-011-1/+0
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| * riscv: use linux/uaccess.h, not asm/uaccess.h...Al Viro2017-12-051-1/+0
* | riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-081-1/+1
* | RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-011-1/+1
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| * | RISC-V: io.h: type fixes for warningsOlof Johansson2017-11-301-1/+1
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* / RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-302-0/+24
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* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-271-0/+4
* RISC-V: Paging and MMUPalmer Dabbelt2017-09-271-0/+282
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-271-0/+92
* RISC-V: ELF and module implementationPalmer Dabbelt2017-09-271-0/+37
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-271-0/+70
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