summaryrefslogtreecommitdiffstats
path: root/arch/riscv (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: Fix fully ordered LR/SC xchg[8|16]() implementationsAlexandre Ghiti2024-05-301-10/+12
* riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernelNam Cao2024-05-301-1/+1
* riscv: prevent pt_regs corruption for secondary idle threadsSergey Matyukevich2024-05-302-3/+2
* Merge tag 'riscv-for-linus-6.10-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-05-2420-181/+294
|\
| * riscv: Fix early ftrace nop patchingAlexandre Ghiti2024-05-232-0/+9
| * Merge patch series "riscv: Extension parsing fixes"Palmer Dabbelt2024-05-233-7/+45
| |\
| | * riscv: cpufeature: Fix extension subset checkingCharlie Jenkins2024-05-221-1/+1
| | * riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins2024-05-223-6/+44
| * | riscv: mm: accelerate pagefault when badaccessKefeng Wang2024-05-231-2/+2
| * | riscv: uaccess: Relax the threshold for fast pathXiao Wang2024-05-231-1/+1
| * | riscv: uaccess: Allow the last potential unrolled copyXiao Wang2024-05-231-1/+1
| * | riscv: typo in comment for get_f64_regXingyou Chen2024-05-231-1/+1
| * | Use bool value in set_cpu_online()Zhao Ke2024-05-231-1/+1
| * | Merge patch series "riscv: fix debug_pagealloc"Palmer Dabbelt2024-05-232-6/+25
| |\ \
| | * | riscv: rewrite __kernel_map_pages() to fix sleeping in invalid contextNam Cao2024-05-221-6/+22
| | * | riscv: force PAGE_SIZE linear mapping if debug_pagealloc is enabledNam Cao2024-05-221-0/+3
| | |/
| * | riscv: stacktrace: fixed walk_stackframe()Matthew Bystrin2024-05-231-6/+14
| * | ftrace: riscv: move from REGS to ARGSPuranjay Mohan2024-05-235-141/+143
| * | Merge patch series "riscv: access_ok() optimization"Palmer Dabbelt2024-05-232-4/+1
| |\ \
| | * | riscv: Define TASK_SIZE_MAX for __access_ok()Samuel Holland2024-05-161-0/+1
| | * | riscv: Remove PGDIR_SIZE_L3 and TASK_SIZE_MINSamuel Holland2024-05-162-4/+0
| | |/
| * | riscv: do not select MODULE_SECTIONS by defaultQingfang Deng2024-05-231-1/+1
| * | riscv: show help string for riscv-specific targetsEmil Renner Berthing2024-05-231-0/+17
| * | riscv: make image compression configurableEmil Renner Berthing2024-05-233-10/+33
* | | Merge tag 'mm-nonmm-stable-2024-05-22-17-30' of git://git.kernel.org/pub/scm/...Linus Torvalds2024-05-235-0/+49
|\ \ \ | |/ / |/| |
| * | riscv: add support for kernel-mode FPUSamuel Holland2024-05-195-0/+49
* | | Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2024-05-2235-666/+615
|\ \ \
| * | | riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800Inochi Amaoto2024-05-131-0/+1
| * | | Merge patch series "riscv: ASID-related and UP-related TLB flush enhancements"Palmer Dabbelt2024-04-3015-151/+113
| |\ \ \
| | * | | riscv: mm: Always use an ASID to flush mm contextsSamuel Holland2024-04-291-2/+1
| | * | | riscv: mm: Preserve global TLB entries when switching contextsSamuel Holland2024-04-291-1/+1
| | * | | riscv: mm: Make asid_bits a local variableSamuel Holland2024-04-291-2/+1
| | * | | riscv: mm: Use a fixed layout for the MM context IDSamuel Holland2024-04-293-8/+4
| | * | | riscv: mm: Introduce cntx2asid/cntx2version helper macrosSamuel Holland2024-04-293-7/+10
| | * | | riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland2024-04-293-1/+8
| | * | | riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vmaSamuel Holland2024-04-293-25/+29
| | * | | riscv: mm: Combine the SMP and UP TLB flush codeSamuel Holland2024-04-293-33/+5
| | * | | riscv: Only send remote fences when some other CPU is onlineSamuel Holland2024-04-292-2/+6
| | * | | riscv: mm: Broadcast kernel TLB flushes only when neededSamuel Holland2024-04-291-13/+5
| | * | | riscv: Use IPIs for remote cache/TLB flushes by defaultSamuel Holland2024-04-297-47/+37
| | * | | riscv: Factor out page table TLB synchronizationSamuel Holland2024-04-291-18/+13
| | * | | riscv: Flush the instruction cache during SMP bringupSamuel Holland2024-04-291-3/+4
| | | |/ | | |/|
| * | | riscv: select ARCH_HAS_FAST_MULTIPLIERJisheng Zhang2024-04-301-0/+1
| * | | Merge patch series "riscv: enable lockless lockref implementation"Palmer Dabbelt2024-04-302-0/+19
| |\ \ \
| | * | | riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release}Jisheng Zhang2024-04-241-0/+18
| | * | | riscv: select ARCH_USE_CMPXCHG_LOCKREFJisheng Zhang2024-04-241-0/+1
| * | | | riscv: mm: still create swiotlb buffer for kmalloc() bouncing if requiredJisheng Zhang2024-04-302-2/+16
| * | | | riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_initDawei Li2024-04-301-2/+2
| * | | | riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabledDawei Li2024-04-301-2/+2
| * | | | Merge patch series "riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX ...Palmer Dabbelt2024-04-306-9/+159
| |\ \ \ \
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-14 10:33:30 +0100