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* treewide: kzalloc() -> kcalloc()Kees Cook2018-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kzalloc() function has a 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a * b, gfp) as well as handling cases of: kzalloc(a * b * c, gfp) with: kzalloc(array3_size(a, b, c), gfp) as it's slightly less ugly than: kzalloc_array(array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: kzalloc(4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ type TYPE; expression THING, E; @@ ( kzalloc( - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | kzalloc( - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression COUNT; typedef u8; typedef __u8; @@ ( kzalloc( - sizeof(u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(__u8) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(unsigned char) * (COUNT) + COUNT , ...) | kzalloc( - sizeof(u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(__u8) * COUNT + COUNT , ...) | kzalloc( - sizeof(char) * COUNT + COUNT , ...) | kzalloc( - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ identifier SIZE, COUNT; @@ - kzalloc + kcalloc ( - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( kzalloc( - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | kzalloc( - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( kzalloc( - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | kzalloc( - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ identifier STRIDE, SIZE, COUNT; @@ ( kzalloc( - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | kzalloc( - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression E1, E2, E3; constant C1, C2, C3; @@ ( kzalloc(C1 * C2 * C3, ...) | kzalloc( - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | kzalloc( - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | kzalloc( - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( kzalloc(sizeof(THING) * C2, ...) | kzalloc(sizeof(TYPE) * C2, ...) | kzalloc(C1 * C2 * C3, ...) | kzalloc(C1 * C2, ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - kzalloc + kcalloc ( - (E1) * E2 + E1, E2 , ...) | - kzalloc + kcalloc ( - (E1) * (E2) + E1, E2 , ...) | - kzalloc + kcalloc ( - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
* arch/sh: pcie-sh7786: handle non-zero DMA offsetThomas Petazzoni2018-04-131-0/+8
| | | | | | | | | | | | | | | | | On SuperH, the base of the physical memory might be different from zero. In this case, PCI address zero will map to a non-zero physical address. In order to make sure that the DMA mapping API takes care of this DMA offset, we must fill in the dev->dma_pfn_offset field for PCI devices. This gets done in the pcibios_bus_add_device() hook, called for each new PCI device detected. The dma_pfn_offset global variable is re-calculated for every PCI controller available on the platform, but that's not an issue because its value will each time be exactly the same, as it only depends on the memory start address and memory size. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
* arch/sh: pcie-sh7786: adjust the memory mappingThomas Petazzoni2018-04-131-5/+14
| | | | | | | | | | | | | | | | | | | | | | The code setting up the PCI -> SuperHighway mapping doesn't take into account the fact that the address stored in PCIELARx must be aligned with the size stored in PCIELAMRx. For example, when your physical memory starts at 0x0800_0000 (128 MB), a size of 64 MB or 128 MB is fine. However, if you have 256 MB of memory, it doesn't work because the base address is not aligned on the size. In such situation, we have to round down the base address to make sure it is aligned on the size of the area. For for a 0x0800_0000 base address with 256 MB of memory, we will round down to 0x0, and extend the size of the mapping to 512 MB. This allows the mapping to work on platforms that have 256 MB of RAM. The current setup would only work with 128 MB of RAM or less. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
* arch/sh: pcie-sh7786: adjust PCI MEM and IO regionsThomas Petazzoni2018-04-131-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current definition of the PCIe IO and MEM resources for SH7786 doesn't match what the datasheet says. For example, for PCIe0 0xfe100000 is advertised by the datasheet as a PCI IO region, while 0xfd000000 is advertised as a PCI MEM region. The code currently inverts the two. The SH4A_PCIEPARL and SH4A_PCIEPTCTLR registers allow to define the base address and role of the different regions (including whether it's a MEM or IO region). However, practical experience on a SH7786 shows that if 0xfe100000 is used for LEL and 0xfd000000 for IO, a PCIe device using two MEM BARs cannot be accessed at all. Simply using 0xfe100000 for IO and 0xfd000000 for MEM makes the PCIe device accessible. It is very likely that this was never seen because there are two other PCI MEM region listed in the resources. However, for different reasons, none of the two other MEM regions are usable on the specific SH7786 platform the problem was encountered. Therefore, the last MEM region at 0xfe100000 was used to place the BARs, making the device non-functional. This commit therefore adjusts those PCI MEM and IO resources definitions so that they match what the datasheet says. They have only been tested with PCIe 0. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
* arch/sh: pcie-sh7786: exclude unusable PCI MEM areasThomas Petazzoni2018-04-131-0/+12
| | | | | | | | | | | | | | Depending on the physical memory layout, some PCI MEM areas are not usable. According to the SH7786 datasheet, the PCI MEM area from 1000_0000 to 13FF_FFFF is only usable if the physical memory layout (in MMSELR) is 1, 2, 5 or 6. In all other configurations, this PCI MEM area is not usable (because it overlaps with DRAM). Therefore, this commit adjusts the PCI SH7786 initialization to mark the relevant PCI resource as IORESOURCE_DISABLED if we can't use it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
* arch/sh: pcie-sh7786: mark unavailable PCI resource as disabledThomas Petazzoni2018-04-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Some PCI MEM resources are marked as IORESOURCE_MEM_32BIT, which means they are only usable when the SH core runs in 32-bit mode. In 29-bit mode, such memory regions are not usable. The existing code for SH7786 properly skips such regions when configuring the PCIe controller registers. However, because such regions are still described in the resource array, the pcibios_scanbus() function in the SuperH pci.c will register them to the PCI core. Due to this, the PCI core will allocate MEM areas from this resource, and assign BARs pointing to this area, even though it's unusable. In order to prevent this from happening, we mark such regions as IORESOURCE_DISABLED, which tells the SuperH pci.c pcibios_scanbus() function to skip them. Note that we separate marking the region as disabled from skipping it, because other regions will be marked as disabled in follow-up patches. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
* sh/PCI: Remove __init optimisations from IRQ mapping functions/dataMatthew Minter2017-08-031-1/+1
| | | | | | | | | | | | | | | | Currently many IRQ mapping functions and data structures use the __init and __initdata optimisations. These result in the relevant functions being innaccessible after boot time. However for deferred IRQ assignment it is important to have access to these functions at PCI device enable time. Therefore, remove the optimisation from the relevant data structures and functions to prepare for deferred IRQ assignment. Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
* async: rename and redefine async_func_ptrLai Jiangshan2013-03-121-1/+1
| | | | | | | | | | | | | A function type is typically defined as typedef ret_type (*func)(args..) but async_func_ptr is not. Redefine it. Also rename async_func_ptr to async_func_t for _func_t suffix is more generic. Signed-off-by: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Arjan van de Ven <arjan@linux.intel.com>
* ARCH: drivers remove __dev* attributes.Greg Kroah-Hartman2013-01-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes up all of the smaller arches that had __dev* markings for their platform-specific drivers. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Mikael Starvik <starvik@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: David Howells <dhowells@redhat.com> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Michal Simek <monstr@monstr.eu> Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Cc: Jonas Bonn <jonas@southpole.se> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Bob Liu <lliubbo@gmail.com> Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Myron Stowe <myron.stowe@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: "Srivatsa S. Bhat" <srivatsa.bhat@linux.vnet.ibm.com> Cc: Mark Salter <msalter@redhat.com> Cc: Yong Zhang <yong.zhang0@gmail.com> Cc: Michael Holzheu <holzheu@linux.vnet.ibm.com> Cc: Cornelia Huck <cornelia.huck@de.ibm.com> Cc: Jan Glauber <jang@linux.vnet.ibm.com> Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* sh: Convert sh_clk_mstp32_register to sh_clk_mstp_registerNobuhiro Iwamatsu2012-06-281-1/+1
| | | | | | | sh_clk_mstp32_register is deprecated. This convert to sh_clk_mstp_register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: legacy PCI evt2irq migration.Paul Mundt2012-05-181-1/+2
| | | | | | This converts over the legacy PCI IRQs to evt2irq() backed hwirq lookups. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.Ralf Baechle2011-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aside of the usual motivation for constification, this function has a history of being abused a hook for interrupt and other fixups so I turned this function const ages ago in the MIPS code but it should be done treewide. Due to function pointer passing in varous places a few other functions had to be constified as well. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> To: Anton Vorontsov <avorontsov@mvista.com> To: Chris Metcalf <cmetcalf@tilera.com> To: Colin Cross <ccross@android.com> Acked-by: "David S. Miller" <davem@davemloft.net> To: Eric Miao <eric.y.miao@gmail.com> To: Erik Gilling <konkers@android.com> Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> To: "H. Peter Anvin" <hpa@zytor.com> To: Imre Kaloz <kaloz@openwrt.org> To: Ingo Molnar <mingo@redhat.com> To: Ivan Kokshaysky <ink@jurassic.park.msu.ru> To: Jesse Barnes <jbarnes@virtuousgeek.org> To: Krzysztof Halasa <khc@pm.waw.pl> To: Lennert Buytenhek <kernel@wantstofly.org> To: Matt Turner <mattst88@gmail.com> To: Nicolas Pitre <nico@fluxnic.net> To: Olof Johansson <olof@lixom.net> Acked-by: Paul Mundt <lethal@linux-sh.org> To: Richard Henderson <rth@twiddle.net> To: Russell King <linux@arm.linux.org.uk> To: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-alpha@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-pci@vger.kernel.org Cc: linux-sh@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: sparclinux@vger.kernel.org Cc: x86@kernel.org Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* sh: Fix up async PCIe probing on SMP.Paul Mundt2011-01-281-0/+2
| | | | | | | For the SMP case we run in to a lockup without a full synchronization prior to continuing with the boot. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Support asynchronous initialization of SH-X3 PCIe channels.Paul Mundt2011-01-181-18/+28
| | | | | | | | | SH-X3 controllers all have pretty dire delays needed for PHY wakeup, so we attempt to mitigate the damage by bringing them up asynchronously, simply using the synchronization points for persistent bridge to channel numbering. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Convert to upper/lower_32_bits() helpers.Paul Mundt2010-10-141-2/+2
| | | | | | Instead of hand-rolling our own, just use the generic ones instead. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786.Paul Mundt2010-10-141-2/+21
| | | | | | | | | | The SDK7786 FPGA has secondary control over the PCIe clocks, specifically relating to the slots and oscillator. This ties the FPGA clocks in to the clock framework and balances the refcounting similar to how the primary on-chip clocks are managed. While the on-chip clocks are per-port, the FPGA clock enable/disable is global for the entire block. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: clock framework support for SH7786 PCIe.Paul Mundt2010-09-201-21/+86
| | | | | | | This gets each port handling its MSTP bit, as well as moving the PHY clock management in to the clock framework. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Use I/O accessors consistently in SH7786 PCIe init code.Paul Mundt2010-09-201-17/+18
| | | | | | | | Some of the existing code is flipping between __raw_xxx() and pci_{read,write}_reg(). As the latter are just wrappers for the former, flip over to using them consistently. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Support ports with disabled links on SH7786 PCIe.Paul Mundt2010-09-201-5/+12
| | | | | | | | | Presently we error out if a link is disabled and simply drop the port registration outright. This follows the PPC changes and simply reports on the link state on boot, leaving the port registered, in order to more easily deal with hotplug on future parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Discard initial PCICONF4/5 settings for SH7786 PCIe.Paul Mundt2010-09-201-3/+0
| | | | | | | These settings are properly propagated by the hardware already, so there's no need to bother with them manually. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Support root complex config accesses on SH7786 PCIe.Paul Mundt2010-09-201-5/+24
| | | | | | | | | | | | | | | | | | | | The SH7786 PCIe is presently unable to enumerate itself in root complex mode, and has no visibility through either type 0 or type 1 accesses, despite having a mostly sensible extended config space for each port. Attempts to generate type 0 or type 1 config cycles result in completer aborts, so we're ultimately forced to use SuperHyway transactions instead. As each port has a single port <-> device mapping that resolves for any PCI_SLOT definition, we simply hijack devfn 0 for the SuperHyway transaction and bump up the devfn limit. With enumeration of the root complex now possible, we also need to insert an early fixup to hide the BARs from the kernel. With all of that done, it's now possible to use the pcieport services with all of the PCIe ports, which is the first step to power management support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Give SH7786 PHY some time to settle.Paul Mundt2010-09-191-0/+3
| | | | | | | | | | The spec suggests waiting up to 500ms for the PHY to settle before testing link state, but practice shows that 100ms is sufficient (this is the delay value we also use on the other SH-4A PCI controllers, too). This makes device detection much more reliable, although in the future it should be a bit faster to simply serialize with a TLP IRQ. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'sh/pci-express-integration'Paul Mundt2010-09-071-9/+31
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| * sh: Hook up 3rd memory window for all SH7786 PCIe channels.Paul Mundt2010-09-071-0/+3
| | | | | | | | | | | | | | | | Now that the resource assignment issues are resolved, we can finally wire up the small third memory window -- in the future we may reclaim this for MSI. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Properly wire up channel 2's I/O window on SH7786 PCIe.Paul Mundt2010-09-071-0/+1
| | | | | | | | | | | | | | | | | | An IORESOURCE_IO was missing here, which meant that we weren't properly establishing the I/O window for this particular slot. With this corrected, cards with I/O BARs have them actually assigned and accessible. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Ignore 32-bit windows in 29-bit mode for SH7786 PCIe.Paul Mundt2010-09-071-8/+16
| | | | | | | | | | | | | | | | | | Certain memory windows are only available for 32-bit space, so skip over these in 29-bit mode. This will severely restrict the amount of memory that can be mapped, but since a boot loader bug makes booting in 29-bit mode close to impossible anyways, everything is ok. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Establish a SuperHyway<->PCIe window mapping on SH7786 PCIe.Paul Mundt2010-09-071-1/+1
| | | | | | | | | | | | | | | | This bumps up the low address to match the physical memory windows for SHway<->PCIe transfers. The previous implementation was banking on a 1:1 virt<->phys SHway mapping, which doesn't apply here. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Make SH7786 PCIe port reset logic more aggressive.Paul Mundt2010-09-071-1/+11
| | | | | | | | | | | | | | This attempts a more complete port reset, building on top of the existing approach. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | Merge branch 'sh/pci-express-integration'Paul Mundt2010-08-201-12/+18
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| * sh: Fix up SH7786 PCIe PHY initialization.Paul Mundt2010-08-201-12/+18
| | | | | | | | | | | | | | This brings the clocking and register setting in line with the somewhat factually ambiguous specification. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Fix typos in PCI initialization messageMatt Fleming2010-06-231-1/+1
|/ | | | | | | This typo seems to have been copy and pasted in the PCI initialization code. Replace 'intialization' with 'initialization'. Signed-off-by: Matt Fleming <matt@console-pimps.org>
* include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo2010-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
* sh: Fix up multi-resource mapping for SH7786 PCIe.Paul Mundt2010-02-101-15/+74
| | | | | | | | | | | | This reworks some of the SH7786 PCIe initialization code to dynamically setup and size the various resource windows, as opposed to the original code that simply wired in a couple of them statically. At the same time, we tidy up the initialization code a bit, kill off some read-only register twiddling that was gleaned from the bus analyzer, and also propagate the physical slot/channel mapping. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up SH7786 PCI resource definitions.Paul Mundt2010-02-081-49/+63
| | | | | | | This adds in some of the missing memory resources for channels 1/2 and gets the code building again for the recent changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Handle PCI controller resource conflicts.Paul Mundt2010-02-011-3/+1
| | | | | | | | | register_pci_controller() can fail, but presently is a void function. Change this over to an int so that we can bail early before continuing on with post-registration initialization (such as throwing the controller in to 66MHz mode in the case of the SH7780 host controller). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pci: Initial PCI-Express support for SH7786 Urquell board.Paul Mundt2009-06-171-0/+355
This adds initial support for the PCI-Express module in the SH7786, particularly as it relates to the urquell platform. Presently it is only supported in root complex mode, with endpoint mode still requiring more debugging. 29/32-bit mode and lane configurations are selectable via board mode pins, and are otherwise fixed. Only 4x and 1x PCI channels are presently handled, the PCI bridge still requires additional debugging and stabilization in hardware. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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