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* sh: prefix sh-specific "CCR" and "CCR2" by "SH_"Geert Uytterhoeven2014-03-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | Commit bcf24e1daa94 ("mmc: omap_hsmmc: use the generic config for omap2plus devices"), enabled the build for other platforms for compile testing. sh-allmodconfig now fails with: include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1 This happens because SuperH #defines "CCR", which is one of the enum values in include/linux/omap-dma.h. There's a similar issue with "CCR2" on sh2a. As "CCR" and "CCR2" are too generic names for global #defines, prefix them with "SH_" to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sh: delete __cpuinit usage from all sh filesPaul Gortmaker2013-07-151-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) are flagged as __cpuinit -- so if we remove the __cpuinit from arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the arch/sh uses of the __cpuinit macros from all C files. Currently sh does not have any __CPUINIT used in assembly files. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* Disintegrate asm/system.h for SHDavid Howells2012-03-281-1/+1
| | | | | | | Disintegrate asm/system.h for SH. Signed-off-by: David Howells <dhowells@redhat.com> cc: linux-sh@vger.kernel.org
* sh: Expose physical addressing mode through cpuinfo.Paul Mundt2010-10-261-0/+2
| | | | | | | | | | | CPUs can be in either the legacy 29-bit or 32-bit physical addressing modes. This follows the x86 approach of tracking the phys bits in cpuinfo and exposing it to userspace through procfs. This change was requested to permit kexec-tools to detect the physical addressing mode in order to determine the appropriate address mangling. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: __cpuinit annotate the CPU init path.Paul Mundt2010-04-211-10/+10
| | | | | | | All of the regular CPU init path needs to be __cpuinit annotated for CPU hotplug. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Tidy CPU probing and fixup section annotations.Paul Mundt2010-04-211-2/+2
| | | | | | | | This does a detect_cpu_and_cache_system() -> cpu_probe() rename, tidies up the unused return value, and stuffs it under __cpuinit in preparation for CPU hotplug. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Setup boot CPU VBR early to enable early page faults.Paul Mundt2010-02-171-4/+17
| | | | | | | | | vmemmap and the vmsplit code amongst others need to be able to take page faults much earlier than trap_init() time, so move this in to the early CPU initialization. VBR setup for secondary CPUs is already handled through start_secondary(), so we only need to do this for the boot CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Mass ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-01-261-5/+5
| | | | | | | | | | | The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off the special uncached section and fixmap.Paul Mundt2010-01-211-2/+2
| | | | | | | | Now that cached_to_uncached works as advertized in 32-bit mode and we're never going to be able to map < 16MB anyways, there's no need for the special uncached section. Kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
*-. Merge branches 'sh/xstate', 'sh/hw-breakpoints' and 'sh/stable-updates'Paul Mundt2010-01-131-43/+55
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| | * sh: Kill off dead UBC headers.Paul Mundt2010-01-051-12/+8
| |/ |/| | | | | | | | | Nothing is using these now, so kill them all off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Move over to dynamically allocated FPU context.Paul Mundt2010-01-131-32/+48
|/ | | | | | | | | | | | | | | | | | | | | This follows the x86 xstate changes and implements a task_xstate slab cache that is dynamically sized to match one of hard FP/soft FP/FPU-less. This also tidies up and consolidates some of the SH-2A/SH-4 FPU fragmentation. Now fpu state restorers are commonly defined, with the init_fpu()/fpu_init() mess reworked to follow the x86 convention. The fpu_init() register initialization has been replaced by xstate setup followed by writing out to hardware via the standard restore path. As init_fpu() now performs a slab allocation a secondary lighterweight restorer is also introduced for the context switch. In the future the DSP state will be rolled in here, too. More work remains for math emulation and the SH-5 FPU, which presently uses its own special (UP-only) interfaces. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Make associative cache writes fatal on all SH-4A parts.Paul Mundt2009-12-041-9/+4
| | | | | | | | | Now that associative cache writes are no longer needed by the SH-4/SH-4A cache flush code, associative write support can be explicitly disabled for all SH-4A parts. This makes any associative write throw an exception, as this behaviour can not be assumed to exist on future parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Minor optimisations to FPU handlingStuart Menefy2009-11-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | A number of small optimisations to FPU handling, in particular: - move the task USEDFPU flag from the thread_info flags field (which is accessed asynchronously to the thread) to a new status field, which is only accessed by the thread itself. This allows locking to be removed in most cases, or can be reduced to a preempt_lock(). This mimics the i386 behaviour. - move the modification of regs->sr and thread_info->status flags out of save_fpu() to __unlazy_fpu(). This gives the compiler a better chance to optimise things, as well as making save_fpu() symmetrical with restore_fpu() and init_fpu(). - implement prepare_to_copy(), so that when creating a thread, we can unlazy the FPU prior to copying the thread data structures. Also make sure that the FPU is disabled while in the kernel, in particular while booting, and for newly created kernel threads, In a very artificial benchmark, the execution time for 2500000 context switches was reduced from 50 to 45 seconds. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off legacy UBC wakeup cruft.Paul Mundt2009-10-161-11/+0
| | | | | | | | | | | | This code was added for some ancient SH-4 solution engines with peculiar boot ROMs that did silly things to the UBC MSTP bits. None of these have been in the wild for years, and these days the clock framework wraps up the MSTP bits, meaning that the UBC code is one of the few interfaces that is stomping MSTP bits underneath the clock framework. At this point the risks far outweigh any benefit this code provided, so just kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'master' into sh/cachetlbPaul Mundt2009-08-191-1/+33
|\ | | | | | | | | Conflicts: arch/sh/kernel/Makefile_64
| * sh: delay slot future proofing via EXPMASK on SH-4A parts.Paul Mundt2009-08-151-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements EXPMASK initialization code for SH-4A parts, where it is possible to disable compat features that will go away in newer cores. Presently this includes disabling support for non-nop instructions in the rte delay slot, as well as a sleep instruction being placed in a delay slot (neither of which the kernel does any longer). As a result of this, any future offenders will have illegal slot exceptions generated for them. Associative writes for the memory-mapped cache array are still left enabled, until such a point that special cache operations for SH-4A are provided to move off of the current (and rather dated) SH-4 versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: rework nommu for generic cache.c use.Paul Mundt2009-08-151-2/+0
|/ | | | | | | This does a bit of reorganizing for allowing nommu to use the new and generic cache.c, no functional changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: add weak l2_cache_init function.Kuninori Morimoto2009-06-021-0/+7
| | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move arch_get_unmapped_area() in to arch/sh/mm/mmap.c.Paul Mundt2008-12-221-0/+2
| | | | | | | Now that arch/sh/mm/mmap.c exists, move arch_get_unmapped_area() there. Follows the ARM change. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up section mismatches.Paul Mundt2008-03-061-1/+1
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Encode L1/L2 cache shape in auxvt.Paul Mundt2008-01-281-1/+28
| | | | | | | | | This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Preparation for uncached jumps through PMB.Stuart Menefy2008-01-281-3/+3
| | | | | | | | | | | | Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Disable initial cache flush on SH-5.Paul Mundt2008-01-281-14/+18
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Don't reference UBC code in CPU init on sh64.Paul Mundt2008-01-281-1/+6
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Bring SMP support back from the dead.Paul Mundt2007-09-211-5/+11
| | | | | | | | | | | There was a very preliminary bunch of SMP code scattered around for the SH7604 microcontrollers from way back when, and it has mostly suffered bitrot since then. With the tree already having been slowly getting prepped for SMP, this plugs in most of the remaining platform-independent bits. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support explicit L1 cache disabling.Paul Mundt2007-09-211-4/+7
| | | | | | | | | This reworks the cache mode configuration in Kconfig, and allows for explicit selection of write-back/write-through/off configurations. All of the cache flushing routines are optimized away for the off case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Tidy up dependencies for SH-2 build.Paul Mundt2007-06-111-14/+1
| | | | | | | | | | | | SH-2 can presently get in to some pretty bogus states, so we tidy up the dependencies a bit and get it all building again. This gets us a bit closer to a functional allyesconfig and allmodconfig, though there are still a few things to fix up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: speculative execution support for SH7780.Paul Mundt2007-05-071-0/+19
| | | | | | | | | | SH7780 has a speculative execution mode where it can speculatively perform an instruction fetch for subroutine returns, this allows it to be enabled. There are some various pitfalls associated with this mode, so it's left as depending on CONFIG_EXPERIMENTAL and not enabled by default. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix SH-3 cache entry_mask and way_size calculation.Paul Mundt2007-03-121-3/+17
| | | | | | | | The code for performing the calculation was only in the SH-4 probe path, move it out to the common path so the other parts get this right too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup cpu_data references for the non-boot CPUs.Paul Mundt2007-02-131-15/+15
| | | | | | | There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use a per-cpu ASID cache.Paul Mundt2007-02-131-2/+9
| | | | | | | | Previously this was implemented using a global cache, cache this per-CPU instead and bump up the number of context IDs to match NR_CPUS. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7206 and SH7619 CPU subtypes.Yoshinori Sato2006-12-061-0/+2
| | | | | | | | This implements initial support for the SH7206 (SH-2A) and SH7619 (SH-2) MMU-less CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Calculate shm alignment at runtime.Paul Mundt2006-09-271-0/+5
| | | | | | | Set the SHM alignment at runtime, based off of probed cache desc. Optimize get_unmapped_area() to only colour align shared mappings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Optimized cache handling for SH-4/SH-4A caches.Richard Curnow2006-09-271-1/+15
| | | | | | | | | This reworks some of the SH-4 cache handling code to more easily accomodate newer-style caches (particularly for the > direct-mapped case), as well as optimizing some of the old code. Signed-off-by: Richard Curnow <richard.curnow@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* [PATCH] Don't pass boot parameters to argv_init[]OGAWA Hirofumi2006-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boot cmdline is parsed in parse_early_param() and parse_args(,unknown_bootoption). And __setup() is used in obsolete_checksetup(). start_kernel() -> parse_args() -> unknown_bootoption() -> obsolete_checksetup() If __setup()'s callback (->setup_func()) returns 1 in obsolete_checksetup(), obsolete_checksetup() thinks a parameter was handled. If ->setup_func() returns 0, obsolete_checksetup() tries other ->setup_func(). If all ->setup_func() that matched a parameter returns 0, a parameter is seted to argv_init[]. Then, when runing /sbin/init or init=app, argv_init[] is passed to the app. If the app doesn't ignore those arguments, it will warning and exit. This patch fixes a wrong usage of it, however fixes obvious one only. Signed-off-by: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-171-0/+222
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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