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* perf/x86/rapl: fix AMD event handlingStephane Eranian2022-01-181-3/+6
* perf/x86/rapl: Use CPUID bit on AMD and Hygon partsAndrew Cooper2021-06-011-4/+2
* perf/x86/rapl: Add support for Intel Alder LakeZhang Rui2021-04-191-0/+2
* perf/x86/rapl: Fix psys-energy event on Intel SPR platformZhang Rui2021-02-101-12/+9
* perf/x86/rapl: Only check lower 32bits for RAPL energy countersZhang Rui2021-02-101-5/+8
* perf/x86: fix sysfs type mismatchesSami Tolvanen2020-11-171-13/+1
* perf/x86/rapl: Add AMD Fam19h RAPL supportKim Phillips2020-09-101-0/+1
* perf/x86/rapl: Add support for Intel SPR platformZhang Rui2020-08-141-0/+20
* perf/x86/rapl: Support multiple RAPL unit quirksZhang Rui2020-08-141-9/+15
* perf/x86/rapl: Fix missing psys sysfs attributesZhang Rui2020-08-141-1/+1
* perf/x86/rapl: Add Hygon Fam18h RAPL supportPu Wen2020-07-281-1/+2
* perf/x86/rapl: Add AMD Fam17h RAPL supportStephane Eranian2020-05-281-0/+18
* perf/x86/rapl: Flip logic on default events visibilityStephane Eranian2020-05-281-0/+11
* perf/x86/rapl: Refactor to share the RAPL code between Intel and AMD CPUsStephane Eranian2020-05-281-6/+23
* perf/x86/rapl: Move RAPL support to common x86 codeStephane Eranian2020-05-281-0/+805
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