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* x86/retpoline: Add initial retpoline supportDavid Woodhouse2018-01-123-0/+155
* x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSCTom Lendacky2018-01-091-0/+1
* x86/cpu/AMD: Make LFENCE a serializing instructionTom Lendacky2018-01-091-0/+2
* x86/cpufeatures: Add X86_BUG_SPECTRE_V[12]David Woodhouse2018-01-061-0/+2
* x86/pti: Rename BUG_CPU_INSECURE to BUG_CPU_MELTDOWNThomas Gleixner2018-01-051-1/+1
* x86/alternatives: Add missing '\n' at end of ALTERNATIVE inline asmDavid Woodhouse2018-01-051-2/+2
* x86/kaslr: Fix the vaddr_end messThomas Gleixner2018-01-051-1/+7
* x86/mm: Map cpu_entry_area at the same place on 4/5 levelThomas Gleixner2018-01-041-2/+2
* x86/mm: Set MODULES_END to 0xffffffffff000000Andrey Ryabinin2018-01-041-1/+1
* x86/dumpstack: Fix partial register dumpsJosh Poimboeuf2018-01-031-4/+13
* x86/mm: Remove preempt_disable/enable() from __native_flush_tlb()Thomas Gleixner2017-12-311-6/+8
* x86/ldt: Make the LDT mapping ROThomas Gleixner2017-12-231-0/+2
* x86/mm/dump_pagetables: Allow dumping current pagetablesThomas Gleixner2017-12-231-1/+1
* x86/mm/dump_pagetables: Check user space page table for WX pagesThomas Gleixner2017-12-231-0/+1
* x86/mm: Clarify the whole ASID/kernel PCID/user PCID namingPeter Zijlstra2017-12-231-12/+43
* x86/mm: Use INVPCID for __native_flush_tlb_single()Dave Hansen2017-12-232-1/+23
* x86/mm: Use/Fix PCID to optimize user/kernel switchesPeter Zijlstra2017-12-233-13/+90
* x86/mm: Allow flushing for future ASID switchesDave Hansen2017-12-231-8/+29
* x86/pti: Map the vsyscall page if neededAndy Lutomirski2017-12-231-0/+1
* x86/pti: Put the LDT in its own PGD if PTI is onAndy Lutomirski2017-12-233-13/+73
* x86/mm/64: Make a full PGD-entry size hole in the memory mapAndy Lutomirski2017-12-231-2/+2
* x86/cpu_entry_area: Add debugstore entries to cpu_entry_areaThomas Gleixner2017-12-232-0/+49
* x86/mm/pti: Populate user PGDDave Hansen2017-12-231-1/+8
* x86/mm/pti: Allocate a separate user PGDDave Hansen2017-12-231-0/+11
* x86/mm/pti: Allow NX poison to be set in p4d/pgdDave Hansen2017-12-231-2/+12
* x86/mm/pti: Add mapping helper functionsDave Hansen2017-12-232-1/+97
* x86/mm/pti: Add infrastructure for page table isolationThomas Gleixner2017-12-231-0/+14
* x86/cpufeatures: Add X86_BUG_CPU_INSECUREThomas Gleixner2017-12-232-2/+9
* init: Invoke init_espfix_bsp() from mm_init()Thomas Gleixner2017-12-221-3/+4
* x86/cpu_entry_area: Move it out of the fixmapThomas Gleixner2017-12-225-54/+59
* x86/cpu_entry_area: Move it to a separate unitThomas Gleixner2017-12-222-40/+53
* x86/mm: Create asm/invpcid.hPeter Zijlstra2017-12-222-48/+54
* x86/mm: Put MMU to hardware ASID translation in one placeDave Hansen2017-12-221-11/+18
* x86/mm: Remove hard-coded ASID limit checksDave Hansen2017-12-221-2/+18
* x86/mm: Move the CR3 construction functions to tlbflush.hDave Hansen2017-12-222-28/+27
* x86/mm: Add comments to clarify which TLB-flush functions are supposed to flu...Peter Zijlstra2017-12-221-2/+21
* x86/mm: Remove superfluous barriersPeter Zijlstra2017-12-221-7/+1
* x86/microcode: Dont abuse the TLB-flush interfacePeter Zijlstra2017-12-221-13/+6
* x86/entry: Rename SYSENTER_stack to CPU_ENTRY_AREA_entry_stackDave Hansen2017-12-223-9/+9
* x86/ldt: Prevent LDT inheritance on execThomas Gleixner2017-12-221-7/+14
* x86/ldt: Rework lockingPeter Zijlstra2017-12-222-1/+5
* arch, mm: Allow arch_dup_mmap() to failThomas Gleixner2017-12-221-2/+2
* x86/cpufeatures: Make CPU bugs stickyThomas Gleixner2017-12-172-2/+4
* x86/paravirt: Provide a way to check for hypervisorsThomas Gleixner2017-12-171-10/+15
* x86/entry/64: Make cpu_entry_area.tss read-onlyAndy Lutomirski2017-12-174-16/+20
* x86/entry: Clean up the SYSENTER_stack codeAndy Lutomirski2017-12-172-1/+10
* x86/entry/64: Remove the SYSENTER stack canaryAndy Lutomirski2017-12-171-1/+0
* x86/entry/64: Move the IST stacks into struct cpu_entry_areaAndy Lutomirski2017-12-171-0/+12
* x86/entry/64: Create a per-CPU SYSCALL entry trampolineAndy Lutomirski2017-12-171-0/+2
* x86/entry/64: Use a per-CPU trampoline stack for IDT entriesAndy Lutomirski2017-12-172-2/+3
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