| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | perf/x86/rapl: Use CPUID bit on AMD and Hygon parts | Andrew Cooper | 2021-06-01 | 1 | -0/+4 |
| * | x86/cpu/hygon: Set __max_die_per_package on Hygon | Pu Wen | 2021-03-06 | 1 | -2/+2 |
| * | x86/cpu/amd: Remove dead code for TSEG region remapping | Arvind Sankar | 2020-12-08 | 1 | -20/+0 |
| * | x86/CPU/AMD: Save AMD NodeId as cpu_die_id | Yazen Ghannam | 2020-11-19 | 1 | -6/+5 |
| * | locking/seqlock, headers: Untangle the spaghetti monster | Peter Zijlstra | 2020-08-06 | 1 | -0/+1 |
| * | x86: Remove X86_FEATURE_MFENCE_RDTSC | Josh Poimboeuf | 2019-07-22 | 1 | -18/+3 |
| * | x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors | Pu Wen | 2019-03-23 | 1 | -0/+5 |
| * | x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana | Pu Wen | 2018-09-27 | 1 | -0/+3 |
| * | x86/cpu: Create Hygon Dhyana architecture support file | Pu Wen | 2018-09-27 | 1 | -0/+405 |
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