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path: root/arch/x86/kernel/cpu/intel.c (follow)
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* x86: add hooks for kmemcheckVegard Nossum2009-06-151-0/+23
* x86: don't call read_apic_id if !cpu_has_apicYinghai Lu2009-05-181-3/+3
* Merge branch 'linus' into x86/coreIngo Molnar2009-03-281-1/+7
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| * Merge branch 'core/percpu' into percpu-cpumask-x86-for-linus-2Ingo Molnar2009-03-271-3/+14
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| * | x86: set X86_FEATURE_TSC_RELIABLEIngo Molnar2009-02-261-1/+7
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*-----. | | Merge branches 'x86/apic', 'x86/asm', 'x86/cleanups', 'x86/debug', 'x86/kconf...Ingo Molnar2009-03-141-1/+6
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| | | * | x86, 32-bit: also use cpuinfo_x86's x86_{phys,virt}_bits membersJan Beulich2009-03-131-0/+5
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| | * | x86: move various CPU initialization objects into .cpuinit.rodataJan Beulich2009-03-121-1/+1
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* | | x86: remove smp_apply_quirks()/smp_checks()Yinghai Lu2009-03-081-0/+25
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*-. \ Merge branches 'x86/asm', 'x86/cleanups' and 'x86/headers' into x86/coreIngo Molnar2009-02-201-2/+2
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| | * | x86: use symbolic constants for MSR_IA32_MISC_ENABLE bitsVegard Nossum2009-02-201-2/+2
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* | | x86, apic: remove duplicate asm/apic.h inclusionsIngo Molnar2009-02-171-1/+0
* | | x86, apic: remove genapic.hIngo Molnar2009-02-171-1/+1
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* | Merge branch 'linus' into x86/apicIngo Molnar2009-02-131-0/+3
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| * x86: add clflush before monitor for Intel 7400 seriesPallipadi, Venkatesh2009-02-091-0/+3
* | x86: remove mach_apic.hIngo Molnar2009-01-291-1/+1
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*---. | Merge branches 'x86/asm', 'x86/cleanups', 'x86/cpudetect', 'x86/debug', 'x86/...Ingo Molnar2009-01-281-1/+13
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| | | * x86: correct the CPUID pattern for MSR_IA32_MISC_ENABLE availabilityH. Peter Anvin2009-01-261-1/+1
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| | * x86: handle PAT more like other CPU featuresH. Peter Anvin2009-01-241-0/+12
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* | x86: unmask CPUID levels on Intel CPUs, fixIngo Molnar2009-01-261-8/+11
* | x86: unmask CPUID levels on Intel CPUsH. Peter Anvin2009-01-221-0/+10
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* Merge branch 'x86/tsc' into tracing/coreIngo Molnar2008-12-251-1/+17
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| * Merge branch 'x86/ptrace' into x86/tscIngo Molnar2008-12-231-2/+1
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| * | x86: fix intel x86_64 llc_shared_map/cpu_llc_id anomoliesSuresh Siddha2008-12-191-1/+7
| * | x86: support always running TSC on Intel CPUsVenki Pallipadi2008-12-161-0/+10
* | | x86, bts: provide in-kernel branch-trace interfaceMarkus Metzger2008-12-121-4/+0
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* | x86, bts: DS and BTS initializationMarkus Metzger2008-11-101-2/+1
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* x86: print out apic id in hex formatYinghai Lu2008-10-161-1/+1
* x86: extended "flags" to show virtualization HW feature in /proc/cpuinfoSheng Yang2008-09-101-0/+41
* x86: intel.c put workaround for old cpus togetherYinghai Lu2008-09-101-94/+98
* x86: make intel.c have 64-bit support codeYinghai Lu2008-09-101-36/+83
* Merge branch 'x86/pebs' into x86/unify-cpu-detectIngo Molnar2008-09-101-1/+2
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| * Merge branch 'linus' into x86/pebsIngo Molnar2008-07-251-0/+14
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| * | x86, ptrace: PEBS supportMarkus Metzger2008-05-121-1/+2
* | | x86: little clean up of intel.c/intel_64.cYinghai Lu2008-09-081-4/+3
* | | Merge branch 'x86/x2apic' into x86/coreIngo Molnar2008-09-051-3/+10
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| * | | x86: use cpuid vector 0xb when available for detecting cpu topologySuresh Siddha2008-08-231-3/+10
* | | | x86: remove cpu_vendor_devYinghai Lu2008-09-041-1/+2
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* | | x86: move cmpxchg fallbacks to a generic placeThomas Petazzoni2008-08-181-64/+0
* | | x86: make movsl_mask definition non-CPU specificThomas Petazzoni2008-08-181-7/+0
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* | x86: APIC: remove apic_write_around(); use alternativesMaciej W. Rozycki2008-07-181-0/+10
* | x86: fix numaq_tsc_disable callingYinghai Lu2008-07-131-0/+4
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* x86: clean up cpu capabilities in arch/x86/kernel/cpu/intel.cIngo Molnar2008-04-171-7/+7
* x86: coding style fixes to arch/x86/kernel/cpu/intel.cPaolo Ciarrocchi2008-04-171-40/+43
* x86: use ELF section to list CPU vendor specific codeThomas Petazzoni2008-04-171-6/+3
* x86: add include to cpu/intel.cHarvey Harrison2008-02-041-0/+1
* x86: move MWAIT idle check to generic CPU initialization on 32-bitAndi Kleen2008-01-301-1/+0
* x86: move X86_FEATURE_CONSTANT_TSC into early cpu feature detectionAndi Kleen2008-01-301-7/+6
* x86: lfence fixIngo Molnar2008-01-301-1/+1
* x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUsAndi Kleen2008-01-301-1/+2